- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄224103 > K4T1G044QC-ZCLE6 256M X 4 DDR DRAM, 0.45 ns, PBGA60 PDF資料下載
參數(shù)資料
| 型號(hào)： | K4T1G044QC-ZCLE6 |
| 元件分類： | DRAM |
| 英文描述： | 256M X 4 DDR DRAM, 0.45 ns, PBGA60 |
| 封裝： | ROHS COMPLIANT, FBGA-60 |
| 文件頁數(shù)： | 14/26頁 |
| 文件大?。?/td> | 487K |
| 代理商： | K4T1G044QC-ZCLE6 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁當(dāng)前第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁
DDR2 SDRAM
K4T1G044QC
K4T1G084QC
Rev. 1.1 June 2007
21 of 26
4. Differential data strobe
DDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on the setting of the EMRS “Enable DQS” mode
bit; timing advantages of differential mode are realized in system design. The method by which the DDR2 SDRAM pin timings are measured is mode
dependent. In single ended mode, timing relationships are measured relative to the rising or falling edges of DQS crossing at VREF. In differential mode,
these timing relationships are measured relative to the crosspoint of DQS and its complement, DQS. This distinction in timing methods is guaranteed by
design and characterization. Note that when differential data strobe mode is disabled via the EMRS, the complementary pin, DQS, must be tied externally
to VSS through a 20 ohm to 10 K ohm resisor to insure proper operation.
5. AC timings are for linear signal transitions.
6. These parameters guarantee device behavior, but they are not necessarily tested on each device. They may be guaranteed by device design or tester
correlation.
7. All voltages are referenced to VSS.
8. Tests for AC timing, IDD, and electrical (AC and DC) characteristics, may be conducted at nominal reference/supply voltage levels, but the related
specifications and device operation are guaranteed for the full voltage range specified.
tDS
tDH
tWPRE
tWPST
tDQSH
tDQSL
DQS
D
DMin
DQS/
DQ
DM
tDH
<Data input (write) timing>
DMin
D
DQS
VIL(ac)
VIH(ac)
VIL(ac)
VIH(ac)
VIL(dc)
VIH(dc)
VIL(dc)
VIH(dc)
tCH
tCL
CK
CK/CK
DQS/DQS
DQ
DQS
tRPST
Q
tRPRE
tDQSQmax
tQH
tDQSQmax
<Data output (read) timing>
Q
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| K4T56163QI-ZLD50 | 16M X 16 SYNCHRONOUS DRAM, 0.5 ns, PBGA84 |
| K5A3240YT | Multi-Chip Package MEMORY 32M Bit (4Mx8/2Mx16) Dual Bank NOR Flash Memory / 4M(512Kx8/256Kx16) Full CMOS SRAM |
| K6R1004C1C | 256Kx4 Bit (with OE) High-Speed CMOS Static RAM(5.0V Operating). |
| K6R1004C1C-I | 256Kx4 Bit (with OE) High-Speed CMOS Static RAM(5.0V Operating). |
| K6R1004C1C-I10 | 256Kx4 Bit (with OE) High-Speed CMOS Static RAM(5.0V Operating). |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| K4T1G044QE | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1Gb E-die DDR2 SDRAM |
| K4T1G044QE-HCLE6 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1Gb E-die DDR2 SDRAM |
| K4T1G044QE-HCLE7 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1Gb E-die DDR2 SDRAM |
| K4T1G044QE-HCLF7 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1Gb E-die DDR2 SDRAM |
| K4T1G044QF | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1Gb F-die DDR2 SDRAM |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。