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參數資料
| 型號： | K4T1G044QC-ZCLE6 |
| 元件分類： | DRAM |
| 英文描述： | 256M X 4 DDR DRAM, 0.45 ns, PBGA60 |
| 封裝： | ROHS COMPLIANT, FBGA-60 |
| 文件頁數： | 13/26頁 |
| 文件大?。?/td> | 487K |
| 代理商： | K4T1G044QC-ZCLE6 |
DDR2 SDRAM
K4T1G044QC
K4T1G084QC
Rev. 1.1 June 2007
20 of 26
1. Slew Rate Measurement Levels
a. Output slew rate for falling and rising edges is measured between VTT - 250 mV and VTT + 250 mV for single ended signals.
For differential signals (e.g. DQS - DQS) output slew rate is measured between DQS - DQS = -500 mV and DQS - DQS = +500mV.
Output slew rate is guaranteed by design, but is not necessarily tested on each device.
b. Input slew rate for single ended signals is measured from dc-level to ac-level: from VIL(dc) to VIH(ac) for rising edges and from VIH(dc) and VIL(ac)
for falling edges.
For differential signals (e.g. CK - CK) slew rate for rising edges is measured from CK - CK = -250 mV to CK - CK = +500 mV (250mV to -500 mV
for falling edges).
c. VID is the magnitude of the difference between the input voltage on CK and the input voltage on CK, or between DQS and DQS for differential
strobe.
2. DDR2 SDRAM AC timing reference load
Following figure represents the timing reference load used in defining the relevant timing parameters of the part. It is not intended to be either a precise
representation of the typical system environment or a depiction of the actual load presented by a production tester. System designers will use IBIS or
other simulation tools to correlate the timing reference load to a system environment. Manufacturers will correlate to their production test conditions (gen-
erally a coaxial transmission line terminated at the tester electronics).
The output timing reference voltage level for single ended signals is the crosspoint with VTT. The output timing reference voltage level for differential sig-
nals is the crosspoint of the true (e.g. DQS) and the complement (e.g. DQS) signal.
3. DDR2 SDRAM output slew rate test load
Output slew rate is characterized under the test conditions as shown in the following figure.
VDDQ
DUT
DQ
DQS
RDQS
Output
VTT = VDDQ/2
25
Timing
reference
point
<AC Timing Reference Load>
VDDQ
DUT
DQ
DQS, DQS
RDQS, RDQS
Output
VTT = VDDQ/2
25
Test point
<Slew Rate Test Load>
14.0 General notes, which may apply for all AC parameters
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