參數(shù)資料
型號(hào): K4T1G044QC-ZCLE6
元件分類: DRAM
英文描述: 256M X 4 DDR DRAM, 0.45 ns, PBGA60
封裝: ROHS COMPLIANT, FBGA-60
文件頁數(shù): 16/26頁
文件大小: 487K
代理商: K4T1G044QC-ZCLE6
DDR2 SDRAM
K4T1G044QC
K4T1G084QC
Rev. 1.1 June 2007
23 of 26
For all input signals the total tDS (setup time) and tDH (hold time) required is calculated by adding the data sheet tDS(base) and tDH(base) value to the
tDS and tDH derating value respectively. Example: tDS (total setup time) = tDS(base) + tDS.
tDS1, tDH1 Derating Values for DDR2-400, DDR2-533(All units in ‘ps’; the note applies to the entire table)
DQS Single-ended Slew Rate
2.0 V/ns
1.5 V/ns
1.0 V/ns
0.9 V/ns
0.8 V/ns
0.7 V/ns
0.6 V/ns
0.5 V/ns
0.4 V/ns
tDS
1
tDH
1
tDS
1
tDH
1
tDS
1
tDH
1
tDS
1
tDH
1
tDS
1
tDH
1
tDS
1
tDH
1
tDS
1
tDH
1
tDS
1
tDH
1
tDS
1
tDH
1
DQ
Slew
rate
V/ns
2.0
188
167
146
125
63
----
1.5
146
167
125
83
42
81
43
-
----
1.0
63
125
42
83
0
-2
1
-7
-13
----
0.9
-
31
69
-11
-14
-13
-18
-27
-29
-45
-
----
0.8
-
-25
-31
-27
-30
-32
-44
-43
-62
-60
-86
----
0.7
-
----
-45
-53
-50
-67
-61
-85
-78
-109
-108
-152
--
0.6
-
----
--
-74
-96
-85
-114
-102
-138
-181
-183
-246
0.5
-
----
-128
-156
-145
-180
-175
-223
-226
-288
0.4
-
----
--
-210
-243
-240
-286
-291
-351
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