參數(shù)資料
型號: ISP1181BDGG
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Full-speed Universal Serial Bus peripheral controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PDSO48
封裝: 6.10 MM, PLASTIC, MO-153, SOT-362-1, TSSOP-48
文件頁數(shù): 44/70頁
文件大?。?/td> 341K
代理商: ISP1181BDGG
Philips Semiconductors
ISP1181B
Full-speed USB peripheral controller
Product data
Rev. 02 — 07 December 2004
44 of 70
9397 750 13958
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
When ISP1181B enters ‘suspend’ state (by setting and clearing bit GOSUSP in the
Mode Register), outputs SUSPEND and CLKOUT change state after approximately
2 ms delay. When NOLAZY = 0, the clock signal on output CLKOUT does not stop,
but changes to the 100 kHz
±
50 % LazyClock frequency.
When resuming from ‘suspend’ state by a positive pulse on input WAKEUP, output
SUSPEND is cleared and the clock signal on CLKOUT is restarted after a 0.5 ms
delay. The timing of the CLKOUT signal at ‘suspend’ and ‘resume’ is given in
Figure 13
.
Fig 12. Oscillator and LazyClock logic.
MGS775
CLKRUN
hardware
configuration
register
CLKDIV[3:0]
NOLAZY
÷
(N + 1)
1
0
N
PLL 8
×
XTAL OSC
LAZYCLOCK
enable
enable
4
NOLAZY
CLKOUT
enable
6 MHz
48 MHz
SUSPEND
.
.
100 (±50 %) kHz
If enabled, the 100 kHz
±
50 % LazyClock frequency will be output on pin CLKOUT during ‘suspend’ state.
Fig 13. CLKOUT signal timing at ‘suspend’ and ‘resume’.
MGS776
WAKEUP
GOSUSP
1.8 to 2.2 ms
0.5 ms
PLL circuit stable
3 to 4 ms
SUSPEND
CLKOUT
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