參數(shù)資料
型號: ISP1181BDGG
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Full-speed Universal Serial Bus peripheral controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PDSO48
封裝: 6.10 MM, PLASTIC, MO-153, SOT-362-1, TSSOP-48
文件頁數(shù): 23/70頁
文件大?。?/td> 341K
代理商: ISP1181BDGG
Philips Semiconductors
ISP1181B
Full-speed USB peripheral controller
Product data
Rev. 02 — 07 December 2004
23 of 70
9397 750 13958
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
12. Commands and registers
The functions and registers of ISP1181B are accessed via commands, which consist
of a command code followed by optional data bytes (read or write action). An
overview of the available commands and registers is given in
Table 13
.
A complete access consists of two phases:
1.
Command phase
: when address bit A0 = 1, the ISP1181B interprets the data on
the lower byte of the bus bits D[7:0] as a command code. Commands without a
data phase are executed immediately.
2.
Data phase (optional)
: when address bit A0 = 0, the ISP1181B transfers the
data on the bus to or from a register or endpoint FIFO. Multi-byte registers are
accessed least significant byte/word first.
The following applies for register or FIFO access in 16-bit bus mode:
The upper byte (bits D15 to D8) in command phase or the undefined byte in data
phase are ignored.
The access of registers is word-aligned: byte access is not allowed.
If the packet length is odd, the upper byte of the last word in an IN endpoint buffer
is
not
transmitted to the host. When reading from an OUT endpoint buffer, the
upper byte of the last word must be ignored by the firmware. The packet length is
stored in the first 2 bytes of the endpoint buffer.
Interrupt Enable
IESUSP
IERESM
SOFTCT
GOSUSP
EXTPUL
WKUPCS
PWROFF
all
enables output INT to signal the suspend state
enables output INT to signal the resume state
enables SoftConnect pull-up resistor to USB bus
a HIGH-to-LOW transition enables the suspend state
selects internal (SoftConnect) or external pull-up resistor
enables wake-up on LOW level of input CS
selects powered-off mode during the suspend state
sending data AA37H unlocks the internal registers for
writing after a resume
Mode
Hardware
Configuration
Unlock
Table 12:
Register
Summary of control bits
…continued
Bit
Function
Table 13:
Name
Initialization commands
Write Control OUT Configuration
Command and register summary
Destination
Code (Hex)
Transaction
[1]
Endpoint Configuration Register
endpoint 0 OUT
Endpoint Configuration Register
endpoint 0 IN
Endpoint Configuration Register
endpoint 1 to 14
Endpoint Configuration Register
endpoint 0 OUT
20
write 1 byte
[2]
Write Control IN Configuration
21
write 1 byte
[2]
Write Endpoint n Configuration
(n = 1 to 14)
Read Control OUT Configuration
22 to 2F
write 1 byte
[2][3]
30
read 1 byte
[2]
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