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參數(shù)資料
| 型號(hào)： | ISP1181BDGG |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線控制器 |
| 英文描述： | Full-speed Universal Serial Bus peripheral controller |
| 中文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PDSO48 |
| 封裝： | 6.10 MM, PLASTIC, MO-153, SOT-362-1, TSSOP-48 |
| 文件頁數(shù)： | 41/70頁 |
| 文件大?。?/td> | 341K |
| 代理商： | ISP1181BDGG |
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Philips Semiconductors
ISP1181B
Full-speed USB peripheral controller
Product data
Rev. 02 — 07 December 2004
41 of 70
9397 750 13958
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
13. Interrupts
Figure 8
shows the interrupt logic of the ISP1181B. Each of the indicated USB events
is logged in a status bit of the Interrupt Register. Corresponding bits in the Interrupt
Enable Register determine whether or not an event will generate an interrupt.
Interrupts can be masked globally by means of the INTENA bit of the Mode Register
(see
Table 19
).
The active level and signalling mode of the INT output is controlled by the INTPOL
and INTLVL bits of the Hardware Configuration Register (see
Table 21
). Default
settings after reset are active LOW and level mode. When pulse mode is selected, a
pulse of 166 ns is generated when the OR-ed combination of all interrupt bits
changes from logic 0 to logic 1.
8
7
EP0OUT
BUSTATUS
A logic 1 indicates the interrupt source: control OUT endpoint.
It monitors the current USB bus status (0 = awake,
1 = suspend).
A logic 1 indicates that an EOT interrupt has occurred for a short
packet.
A logic 1 indicates that an interrupt is issued every 1 ms
because of the Pseudo SOF; after 3 missed SOFs ‘suspend’
state is entered.
A logic 1 indicates that a SOF condition was detected.
A logic 1 indicates that an internal EOT condition was generated
by the DMA Counter reaching zero.
A logic 1 indicates that an ‘a(chǎn)wake’ to ‘suspend’ change of state
was detected on the USB bus.
A logic 1 indicates that a ‘resume’ state was detected.
A logic 1 indicates that a bus reset condition was detected.
6
SP_EOT
5
PSOF
4
3
SOF
EOT
2
SUSPND
1
0
RESUME
RESET
Table 49:
Bit
Interrupt Register: bit description
…continued
Symbol
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ISP1181 | Full-speed Universal Serial Bus Interface Device(全速通用串行總線接口器件) |
| ISP1181DGG | INDUCTOR 4.7NH +-.3NH 0402 SMD |
| ISP1183 | Low-power Universal Serial Bus interface device with DMA |
| ISP1183BS | Low-power Universal Serial Bus interface device with DMA |
| ISP1301 | Universal Serial Bus On-The-Go transceiver |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISP1181BDGG,112 | 功能描述:USB 接口集成電路 DO NOT USE ORDER -T PART RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1181BDGG,118 | 功能描述:USB 接口集成電路 USB 1.1 DEVICE CONTROLLER RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1181BDGG-T | 制造商:ST-Ericsson 功能描述:USB Peripheral Controller 48-Pin TSSOP T/R |
| ISP1181BDGGTM | 功能描述:IC USB HOST CTRL FLL-SPD 48TSSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
| ISP1181BPC | 制造商:ST-Ericsson 功能描述:Full-Speed Universal Serial Bus Peripheral Controller |
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