參數(shù)資料
型號: ISP1181BDGG
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Full-speed Universal Serial Bus peripheral controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PDSO48
封裝: 6.10 MM, PLASTIC, MO-153, SOT-362-1, TSSOP-48
文件頁數(shù): 24/70頁
文件大?。?/td> 341K
代理商: ISP1181BDGG
Philips Semiconductors
ISP1181B
Full-speed USB peripheral controller
Product data
Rev. 02 — 07 December 2004
24 of 70
9397 750 13958
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Read Control IN Configuration
Endpoint Configuration Register
endpoint 0 IN
Endpoint Configuration Register
endpoint 1 to 14
Address Register
Mode Register
31
read 1 byte
[2]
Read Endpoint n Configuration
(n = 1 to 14)
Write/Read Device Address
Write/Read Mode Register
Write/Read Hardware Configuration Hardware Configuration Register
Write/Read Interrupt Enable
Register
Write/Read DMA Configuration
Write/Read DMA Counter
Reset Device
Data flow commands
Write Control OUT Buffer
Write Control IN Buffer
Write Endpoint n Buffer
(n = 1 to 14)
32 to 3F
read 1 byte
[2]
B6/B7
B8/B9
BA/BB
C2/C3
write/read 1 byte
[2]
write/read 1 byte
[2]
write/read 2 bytes
write/read 4 bytes
Interrupt Enable Register
DMA Configuration Register
DMA Counter Register
resets all registers
F0/F1
F2/F3
F6
write/read 2 bytes
write/read 2 bytes
-
illegal: endpoint is read-only
FIFO endpoint 0 IN
FIFO endpoint 1 to 14 (IN endpoints
only)
(00)
01
02 to 0F
-
N
64 bytes
isochronous: N
1023 bytes
interrupt/bulk: N
64 bytes
N
64 bytes
-
isochronous:
N
1023 bytes
[4]
interrupt/bulk: N
64 bytes
-
-
-
Read Control OUT Buffer
Read Control IN Buffer
Read Endpoint n Buffer
(n = 1 to 14)
FIFO endpoint 0 OUT
illegal: endpoint is write-only
FIFO endpoint 1 to 14
(OUTendpoints only)
10
(11)
12 to 1F
Stall Control OUT Endpoint
Stall Control IN Endpoint
Stall Endpoint n
(n = 1 to 14)
Read Control OUT Status
Endpoint 0 OUT
Endpoint 0 IN
Endpoint 1 to 14
40
41
42 to 4F
Endpoint Status Register
endpoint 0 OUT
Endpoint Status Register
endpoint 0 IN
Endpoint Status Register n
endpoint 1 to 14
illegal: IN endpoints only
[5]
FIFO endpoint 0 IN
[5]
FIFO endpoint 1 to 14 (IN endpoints
only)
[5]
FIFO endpoint 0 OUT
illegal
[6]
FIFO endpoint 1 to 14
(OUTendpoints only)
[6]
Endpoint 0 OUT
Endpoint 0 IN
50
read 1 byte
[2]
Read Control IN Status
51
read 1 byte
[2]
Read Endpoint n Status
(n = 1 to 14)
Validate Control OUT Buffer
Validate Control IN Buffer
Validate Endpoint n Buffer
(n = 1 to 14)
Clear Control OUT Buffer
Clear Control IN Buffer
Clear Endpoint n Buffer
(n = 1 to 14)
Unstall Control OUT Endpoint
Unstall Control IN Endpoint
52 to 5F
read 1 byte
[2]
(60)
61
62 to 6F
-
-
[3]
-
[3]
70
(71)
72 to 7F
-
[3]
-
[3]
80
81
-
-
Table 13:
Name
Command and register summary
…continued
Destination
Code (Hex)
Transaction
[1]
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