參數(shù)資料
型號: ISP1161BD
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Full-speed Universal Serial Bus single-chip host and device controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝: 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64
文件頁數(shù): 99/127頁
文件大小: 2762K
代理商: ISP1161BD
Philips Semiconductors
ISP1161
Full-speed USB single-chip host and device controller
Product data
Rev. 01 — 3 July 2001
99 of 130
9397 750 08313
Philips Electronics N.V. 2001. All rights reserved.
14.2.7
Acknowledge Setup
This command acknowledges to the host that a SETUP packet was received. The
arrival of a SETUP packet disables the Validate Buffer and Clear Buffer commands
for the control IN and OUT endpoints. The microprocessor needs to re-enable these
commands by sending an Acknowledge Setup command, see
Section 11.3.6
.
Remark:
The Acknowledge Setup command must be sent to
both
control endpoints
(IN and OUT).
Code (Hex): F4 —
acknowledge setup
Transaction —
none
14.3 General commands
14.3.1
Read Endpoint Error Code
This command returns the status of the last transaction of the selected endpoint, as
stored in the Error Code Register. Each new transaction overwrites the previous
status information. The bit allocation of the Error Code Register is shown in
Table 95
.
Code (Hex): A0 to AF —
read error code (control OUT, control IN, endpoint 1 to 14)
Table 93: Endpoint Status Image Register: bit allocation
Bit
7
Symbol
EPSTAL
EPFULL1
6
5
4
3
2
1
0
EPFULL0
DATA_PID
OVER
WRITE
0
R
SETUPT
CPUBUF
reserved
Reset
Access
0
R
0
R
0
R
0
R
0
R
0
R
0
R
Table 94: Endpoint Status Image Register: bit description
Bit
Symbol
Description
7
EPSTAL
This bit indicates whether the endpoint is stalled or not
(1 = stalled, 0 = not stalled).
6
EPFULL1
A logic 1 indicates that the secondary endpoint buffer is full.
5
EPFULL0
A logic 1 indicates that the primary endpoint buffer is full.
4
DATA_PID
This bit indicates the data PID of the present packet (0 = DATA
PID, 1 = DATA1 PID).
3
OVERWRITE
This bit is set by hardware, a logic 1 indicating that a new Setup
packet has overwritten the previous setup information, before it
was acknowledged or before the endpoint was stalled. This bit is
cleared by reading, if writing the setup data has finished.
Firmware must check this bit before sending an Acknowledge
Setup command or stalling the endpoint. Upon reading a logic 1
the firmware must stop ongoing setup actions and wait for a new
Setup packet.
2
SETUPT
A logic 1 indicates that the buffer contains a Setup packet.
1
CPUBUF
This bit indicates which buffer is currently selected for CPU
access (0 = primary buffer, 1 = secondary buffer).
0
-
reserved
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