參數(shù)資料
型號(hào)： ISP1161BD
廠商： NXP SEMICONDUCTORS
元件分類： 總線控制器
英文描述： Full-speed Universal Serial Bus single-chip host and device controller
中文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝： 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64
文件頁(yè)數(shù)： 104/127頁(yè)
文件大?。?/td> 2762K
代理商： ISP1161BD
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Philips Semiconductors
ISP1161
Full-speed USB single-chip host and device controller
Product data
Rev. 01 — 3 July 2001
104 of 130
9397 750 08313
Philips Electronics N.V. 2001. All rights reserved.
15. Reset
Pin RESET is the hardware reset input of ISP1161. It is active LOW. To reset all
internal logic, the minimum timing requirement is 200 ns.
16. Power supply
ISP1161 can operate at either +5 V or +3.3 V.
When using +5 V as ISP1161’s power supply input: Only V
CC
(pin 56) can be
connected to the +5 V power supply. An application with a +5 V power supply input is
shown in
Figure 41
. ISP1161 has an internal DC/DC regulator to provide +3.3 V for
its internal core. This internal +3.3 V can also be obtained from V
reg(3.3)
(pin 58) to
supply the 1.5 k
pull-up resistor of the DC side upstream port signal D_DP. The
signal D_DP is connected to the standard USB upstream port connector’s pin D+.
When using +3.3 V as the power supply input, the internal DC/DC regulator will be
bypassed. All four power supply pins (V
CC
, V
reg(3.3)
, V
hold1
and V
hold2
) can be used as
power supply input.
The best case is to connect all four power supply pins to the +3.3 V power supply, as
shown in
Figure 42
. If, however you do not want to connect all four, you must at least,
connect the V
CC
and the V
reg(3.3)
to the 3.3 V power supply.
For both +3.3 V and 5 V operation, all four power supply pins should be connected to
a decoupling capacitor.
5
PSOF
A logic 1 indicates that an interrupt is issued every 1 ms
because of the Pseudo SOF; after 3 missed SOFs ‘suspend’
state is entered.
A logic 1 indicates that a SOF condition was detected.
A logic 1 indicates that an internal EOT condition was generated
by the DMA Counter reaching zero.
A logic 1 indicates that an ‘a(chǎn)wake’ to ‘suspend’ change of state
was detected on the USB bus.
A logic 1 indicates that a ‘resume’ state was detected.
A logic 1 indicates that a bus reset condition was detected.
4
3
SOF
EOT
2
SUSPND
1
0
RESUME
RESET
Table 107: Interrupt Register: bit description
…continued
Bit
Symbol
Description
Fig 40. RESET pin usage.
MGT962
RESET
reset from
μ
P
or
not connected
VCC
ISP1161
相關(guān)PDF資料
PDF描述
ISP1161BM Full-speed Universal Serial Bus single-chip host and device controller
ISP1181ABS INDUCTOR 1.0NH +-.3NH FIXED SMD
ISP1181A Full-speed Universal Serial Bus peripheral controller
ISP1181ADGG Full-speed Universal Serial Bus peripheral controller
ISP1181B Full-speed Universal Serial Bus peripheral controller
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ISP1161BM 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Full-speed Universal Serial Bus single-chip host and device controller
ISP1181 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Full-speed Universal Serial Bus interface device
ISP1181A 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Full-speed Universal Serial Bus peripheral controller
ISP1181ABS 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Full-speed Universal Serial Bus peripheral controller
ISP1181ABS,518 功能描述:USB 接口集成電路 USB 1.1 ADV DEVICE RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20
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