參數(shù)資料
型號: ISP1161BD
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Full-speed Universal Serial Bus single-chip host and device controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝: 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64
文件頁數(shù): 15/127頁
文件大?。?/td> 2762K
代理商: ISP1161BD
Philips Semiconductors
ISP1161
Full-speed USB single-chip host and device controller
Product data
Rev. 01 — 3 July 2001
15 of 130
9397 750 08313
Philips Electronics N.V. 2001. All rights reserved.
8.3.2
Register access phases
ISP1161’s register structure is a command-data register pair structure. A complete
register access cycle comprises a command phase followed by a data phase. The
command (also known as the index of a register) points the ISP1161 to the next
register to be accessed. A command is 8 bits long. On a microprocessor’s 16-bit data
bus, a command occupies the lower byte, with the upper byte filled with zeros.
Figure 13
shows a complete 16-bit register access cycle for ISP1161. The
microprocessor writes a command code to the command port, and then reads from or
writes the data word to the data port. Take the example of a microprocessor
attempting to read a chip’s ID, which is saved in the HC’s HcChipID register (27H,
read only) where its command code is 27H, read only. The 16-bit register access
cycle is therefore:
1. Microprocessor writes the command code of 27H (0027H in 16-bit width) to
ISP1161’s HC command port
2. Microprocessor reads the data word of the chip’s ID (6110H) from ISP1161’s HC
data port.
When A1 = 0, microprocessor accesses the HC.
When A1 = 1, microprocessor accesses the DC.
Fig 11. A microprocessor accessing a HC or a DC via an automux switch.
When A0 = 0, microprocessor accesses the data port.
When A0 = 1, microprocessor accesses the command port.
Fig 12. Access to internal control registers.
MGT935
μ
P bus I/F
Host bus I/F
Device bus I/F
AUTOMUX
DC/HC
A1
0
1
MGT936
CMD/DATA
SWITCH
Commands
Control registers
Command register
data port
A0
command port
.
Host or Device
bus I/F
1
0
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