參數(shù)資料
型號: ISP1161BD
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Full-speed Universal Serial Bus single-chip host and device controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝: 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64
文件頁數(shù): 35/127頁
文件大?。?/td> 2762K
代理商: ISP1161BD
Philips Semiconductors
ISP1161
Full-speed USB single-chip host and device controller
Product data
Rev. 01 — 3 July 2001
35 of 130
9397 750 08313
Philips Electronics N.V. 2001. All rights reserved.
The ISO packet for frame N + 1 will be written;
The AT packet for frame N + 1 will be written.
In the next example, the microprocessor is still busy transferring the AT data when the
ISO interrupt of the next frame (N + 1) is raised. As a result, there will be no AT traffic
in frame N + 1. The HC should not raise an AT interrupt in frame N + 1. The AT part is
simply postponed until frame N + 2. On the AT N + 2 interrupt the transfer mechanism
is back to normal operation. This simple mechanism ensures, among other things,
that Control transfers are not dropped systematically from the USB in case of an
overloaded microprocessor.
In the following example the ISO part is still being written while the Start of Frame
(SOF) of the next frame has occurred. This will result in undefined behaviour for the
ISO data on the USB bus in frame N + 1 (depending on the exact timing data is
corrupted or not). The HC should not raise an AT interrupt in frame N + 1.
Fig 30. HC time domain behavior: example 1.
MGT954
(frame N)
(frame N
+
1)
(frame N
+
2)
(frame N
+
3)
read ISO_A(N
1) write ISO_A(N
+
1)
SOF
read AT(N)
write AT(N
+
1)
AT
interrupt
traffic
on USB
ISO
interrupt
Fig 31. HC time domain behavior: example 2.
MGT955
(frame N)
(frame N
+
1)
(frame N
+
2)
(frame N
+
3)
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ISP1181ABS,518 功能描述:USB 接口集成電路 USB 1.1 ADV DEVICE RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20