參數(shù)資料
型號: ISP1161BD
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Full-speed Universal Serial Bus single-chip host and device controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝: 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64
文件頁數(shù): 10/127頁
文件大小: 2762K
代理商: ISP1161BD
Philips Semiconductors
ISP1161
Full-speed USB single-chip host and device controller
Product data
Rev. 01 — 3 July 2001
10 of 130
9397 750 08313
Philips Electronics N.V. 2001. All rights reserved.
[1]
Symbol names with an overscore (e.g. NAME) represent active LOW signals.
XTAL2
44
O
crystal oscillator output (6 MHz); connect a fundamental
mode or third-overtone, parallel-resonant crystal; leave this
pin open when using an external clock source on pin
XTAL1
digital ground
power switching control output for downstream port 1; open
drain output
power switching control output for downstream port 2; open
drain output
USB D- data line for DC’s upstream port
USB D+ data line for DC’s upstream port
USB D- data line for HC’s downstream port 1
USB D+ data line for HC’s downstream port 1
USB D- data line for HC’s downstream port 2
USB D+ data line for HC’s downstream port 2
overcurrent sensing input for HC’s downstream port 1
overcurrent sensing input for HC’s downstream port 2
digital power supply voltage input (3.0 to 3.6 V or
4.75 to 5.25 V). This pin connects to the internal 3.3 V
regulator input. When connected to +5 V, the internal
regulator will output 3.3 V to pins V
reg(3.3)
, V
hold1
and V
hold2
.
When connected to 3.3 V, it will bypass the internal
regulator.
analog ground
internal 3.3 V regulator output; When the V
CC
pin is
connected to +5 V, this pin outputs 3.3 V. When the V
CC
pin
is connected to +3.3 V, then this pin should also be
connected to +3.3 V.
address input; selects command (A0 = 1) or data (A0 = 0)
address input; selects AutoMux switching to DC (A1 = 1) or
AutoMux switching to HC (A1 = 0); see
Table 3
no connection
digital ground
bit 0 of bidirectional data; slew-rate controlled; TTL input;
three-state output
bit 1 of bidirectional data; slew-rate controlled; TTL input;
three-state output
DGND
H_PSW1
45
46
-
O
H_PSW2
47
O
D_DM
D_DP
H_DM1
H_DP1
H_DM2
H_DP2
H_OC1
H_OC2
V
CC
48
49
50
51
52
53
54
55
56
AI/O
AI/O
AI/O
AI/O
AI/O
AI/O
I
I
-
AGND
V
reg(3.3)
57
58
-
-
A0
A1
59
60
I
I
n.c.
DGND
D0
61
62
63
-
-
I/O
D1
64
I/O
Table 2:
Symbol
[1]
Pin description for LQFP64
…continued
Pin
Type
Description
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