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參數(shù)資料
| 型號： | ISP1161BD |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線控制器 |
| 英文描述： | Full-speed Universal Serial Bus single-chip host and device controller |
| 中文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP64 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64 |
| 文件頁數(shù)： | 43/127頁 |
| 文件大小： | 2762K |
| 代理商： | ISP1161BD |
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Philips Semiconductors
ISP1161
Full-speed USB single-chip host and device controller
Product data
Rev. 01 — 3 July 2001
43 of 130
9397 750 08313
Philips Electronics N.V. 2001. All rights reserved.
11.1.2
OUT data transfer
The arrival of the OUT token is detected by the SIE by decoding the PID.
The SIE also checks for the device number and endpoint number and verifies
whether they are ok.
If the endpoint is enabled, the SIE checks the contents of the Endpoint Status
register. If the endpoint is empty, the data from USB is stored to FIFO during the
data phase, else a NAK handshake is sent.
After the data phase, the SIE sends a handshake (ACK) to the host (except for ISO
endpoints).
The SIE updates the contents of the interrupt register, which in turn generates an
interrupt to the microprocessor. The LTR status is updated and the buffer is set to
full in the Endpoint Status Register. For ISO endpoints, interrupt and LTR status
are updated as soon as data is received successfully, since there is no handshake
phase.
On receiving interrupt, the microprocessor reads the interrupt register. It will know
which endpoint has generated the interrupt and reads the content of the
corresponding Endpoint Status register. If the buffer is full, it empties the buffer, so
that data can be received by the SIE at the next OUT token phase.
11.2 Device DMA transfer
11.2.1
For OUT endpoint (external USB host to ISP1161’s DC)
When the internal DMA handler is enabled and at least one buffer (Ping or Pong) is
free, the DREQ2 line is asserted. The external DMA controller then starts negotiating
for the bus with ISP1161. As soon as it has access, it asserts the DACK2 line and
starts writing data. The burst length is programmable. When the number of bytes
equal to the burst length has been written, the DREQ2 line is deasserted. As a result,
the DMA controller deasserts the DACK2 line and releases the bus. At that moment
the whole cycle restarts for the next burst.
When the buffer is full, the DREQ2 line will be de-asserted and the buffer is validated
(which means that it will be sent to the host when the next IN token comes in). When
the DMA controller terminates the DMA transfer by asserting EOT, the buffer is also
validated (even if it is not full). In Auto-reload mode, the DMA handler will
automatically restart by asserting its DREQ2 line as soon as a new buffer is available.
If the Auto-reload mode is off, then the DMA handler will be disabled automatically.
For the next DMA transfer, the DMA handler must be reenabled.
11.2.2
For IN endpoint (ISP1161’s DC to external USB host)
When the internal DMA handler is enabled and at least one buffer is full, the DREQ2
line is asserted. The external DMA controller then starts negotiating for the bus with
other parties and as soon as it has access, it asserts the DACK2 line and starts
reading the data. The burst length is programmable. When the number of bytes equal
to the burst length has been read, the DREQ2 line is deasserted. As a result, the
DMA controller deasserts the DACK2 line and releases the bus. At that moment the
whole cycle restarts for the next burst. When all data are read, the DREQ2 line will be
deasserted and the buffer is cleared (which means that it can be overwritten when a
new packet comes in).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ISP1161BM | Full-speed Universal Serial Bus single-chip host and device controller |
| ISP1181ABS | INDUCTOR 1.0NH +-.3NH FIXED SMD |
| ISP1181A | Full-speed Universal Serial Bus peripheral controller |
| ISP1181ADGG | Full-speed Universal Serial Bus peripheral controller |
| ISP1181B | Full-speed Universal Serial Bus peripheral controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISP1161BM | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Full-speed Universal Serial Bus single-chip host and device controller |
| ISP1181 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Full-speed Universal Serial Bus interface device |
| ISP1181A | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Full-speed Universal Serial Bus peripheral controller |
| ISP1181ABS | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Full-speed Universal Serial Bus peripheral controller |
| ISP1181ABS,518 | 功能描述:USB 接口集成電路 USB 1.1 ADV DEVICE RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
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