參數(shù)資料
型號: ISP1161BD
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Full-speed Universal Serial Bus single-chip host and device controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝: 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64
文件頁數(shù): 116/127頁
文件大小: 2762K
代理商: ISP1161BD
Philips Semiconductors
ISP1161
Full-speed USB single-chip host and device controller
Product data
Rev. 01 — 3 July 2001
116 of 130
9397 750 08313
Philips Electronics N.V. 2001. All rights reserved.
20.3.8
DC multi-cycle burst mode DMA timing
20.3.9
DMA terminated by EOT
Table 122:Dynamic characteristics: DC multi-cycle burst mode DMA timing
Symbol
Parameter
t
RHSH
DREQ2 ON to first RD/WR OFF
t
SLRL
last RD/WR ON to DREQ2 OFF
t
SHAH
last RD/WR OFF to DACK2 OFF
t
RHRL
DMA burst repeat interval
Conditions
Min
22
-
0
180
Typ
-
-
-
-
Max
-
60
-
-
Unit
ns
ns
ns
ns
Fig 53. DC multi-cycle burst mode DMA timing.
MGT977
tRHSH
tSLRL
tRHRL
tSHAH
DREQ2
DACK2
RD or WR
Table 123:Dynamic characteristics: DMA terminated by EOT
Symbol
Parameter
t
ELRL
EOT ON to DREQ2 OFF
Conditions
Min
-
Typ
-
Max
40
Unit
ns
Fig 54. DMA terminated by EOT.
MGT978
tELRL
DREQ2
DACK2
EOT
RD or WR
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