參數(shù)資料
型號(hào)： INT5130CS
廠商： Electronic Theatre Controls, Inc.
英文描述： Integrated Powerline MAC/PHY Transceiver
中文描述： 綜合電力線MAC /物理層收發(fā)器
文件頁(yè)數(shù)： 8/38頁(yè)
文件大?。?/td> 1352K
代理商： INT5130CS
INTELLON CONFIDENTIAL
Rev 8.1
8
ADVANCE INFORMATION
INT5130 Integrated Powerline MAC /PHY Transceiver Technical Data Sheet
AGCENC_N
Input
AGC Encode
An inactive signal (logic 1) applied to this input
selects unitary AGC format. An active signal (logic
0) applied to this input selects encoded AGC format
Test Access Port
TCK
Input
Test Clock
Test Clock for the IEEE 1149.1 JTAG Port
Test Data In
Data In for the IEEE 1149.1 JTAG Port
Test Mode Select
Test Mode Select for the IEEE 1149.1 JTAG Port
Test Data Out
Data Out for the IEEE 1149.1 JTAG Port
Test Reset
This pin will be used to reset the TAP controller. It
should be connected to ground when the JTAG port
is not in use.
TDI
Input
TMS
Input
TDO
Output
TRST_N
Input
System Control
RESET_N
Input
Reset
Resets logic circuitry, but not clock circuitry. Reset
is active low and should be held low for a minimum
of 100 ns.
Clock Input
100 MHz clock input. Driven by an external
oscillator or an external crystal (feedback path for
crystal implementation provided by CLKOUT)
Note:
CLKIN connects directly to the 2.5 V core of the IC
and does not connect to the 3.3 V I/O ring.
Therefore, this pin is not 3.3 or 5 V tolerant.
Clock Output
100 MHz clock feedback path when a crystal is
implemented. This pin should be left as NO
CONNECT if an external oscillator is implemented on
CLKIN.
Note:
CLKOUT connects directly to the 2.5
V core of the IC and does not connect to the 3.3 V
I/O ring. Therefore, this pin is not 3.3 or 5 V
tolerant.
MDI PHY Address Selection
Address select used to compare against the upper
two bits of the MDI Address. These pins share
function with SPIS_CS_N and SPIS_SDI and should
be pulled-up or down with external resistors to set
the appropriate value which is read by the INT5130
during power up.
Management Data Interface/Serial Peripheral
Interface Slave Select.
Selects which PHY management signals are active.
Media Independent Interface/General Purpose
Serial Interface Select.
Selects which PHY data interface signals are active.
CLKIN
Clock Pad
CLKOUT
Clock Pad
MDI_ADRSEL[1:0]
Input
MDI_SPIS_N
Input
MII_GPSI_N
Input
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