參數(shù)資料
型號： INT5130CS
廠商： Electronic Theatre Controls, Inc.
英文描述： Integrated Powerline MAC/PHY Transceiver
中文描述： 綜合電力線MAC /物理層收發(fā)器
文件頁數(shù)： 17/38頁
文件大?。?/td> 1352K
代理商： INT5130CS
INTELLON CONFIDENTIAL
Rev 8.1
17
ADVANCE INFORMATION
INT5130 Integrated Powerline MAC /PHY Transceiver Technical Data Sheet
Data
Data sent over the MII interface consists of N bytes of data transmitted as 2N nibbles.
The de-assertion of the MII_TXEN signals the End Of Frame (EOF) for data transmitted on the
MII_TX[3:0] pins. Likewise, the de-assertion of the MII_RXDV signals the EOF for data transmitted on
MII_RX[3:0].
Figure 10: Partition of Serial Bit Stream to Nibble Stream
MDI Control Interface
The Management Data Interface connects the external host to the INT5130 for purposes of controlling the
INT5130 and gathering status. A specific frame format and protocol definition exists for exchanging
management frames over this interface. A register definition exists as well that specifies a basic register
set with an extension mechanism. The INT5130 implements the basic register set only.
MDI Timing Diagrams
MII_MDCLK
MII_MDIO
t
MDI_RVAL
DATA
Figure 11: MDI Receive Timing Diagram
MACs Serial Bit Stream
First nibble
D0
D1
D2
D3
D4
D6
D5
D7
D0
D1
D2
D3
Second nibble
LSB
MSB
MII
Nibble
Stream
LSB
MSB
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