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參數(shù)資料
| 型號： | IP1001 |
| 廠商： | International Rectifier |
| 英文描述： | Full Function Synchronous Buck Power Block |
| 中文描述： | 全功能的同步降壓電源模塊 |
| 文件頁數(shù)： | 1/18頁 |
| 文件大?。?/td> | 507K |
| 代理商： | IP1001 |
3.3V to 12V input voltage
1
20A maximum load capability, with no derating up to T
PCB
= 90°C
5 bit DAC settable, 0.925V to 2V output voltage range
2
Configurable down to 3.3Vin & up to 3.3Vout with simple external circuit
3
200kHz or 300kHz nominal switching frequency
Optimized for very low power losses
Over & undervoltage protection
Adjustable lossless current limit
Internal features minimize layout sensitivity *
Very small outline 14mm x 14mm x 3mm
Full Function Synchronous Buck Power Block
Integrated Power Semiconductors, Control IC & Passives
The iP1001 is a fully optimized solution for high current synchronous buck applications requiring up to 20A.
The iP1001 is optimized for single-phase applications, and includes a full function fast transient response
PWM control, with an optimized power semiconductor chip-set and associated passives, achieving benchmark
power density. Very few external components are required, including output inductor, input & output capacitors.
Further range of operation to 3.3Vin can be achieved with the addition of a simple external boost circuit, and
operation up to 3.3Vout can be achieved with a simple external voltage divider.
iPOWIR technology offers designers an innovative board space-saving solution for applications requiring high
power densities. iPOWIR technology eases design for applications where component integration offers
benefits in performance and functionality. iPOWIR technology solutions are also optimized internally for layout,
heat transfer and component selection.
Description
iP1001 Power Block
Features
* Although, all of the difficult PCB layout and bypassing issues have been addressed with the internal design of the iPOWIR block, proper layout techniques should be
applied for the design of the power supply board. There are no concerns about unwanted shutdowns common to switching power supplies, if operated as specified. The
iPOWIR block will function normally, but not optimally without any additional input decoupling capacitors. Input decoupling capacitors should be added at Vin pin for stable
and reliable long term operation. No additional bypassing is required on the Vdd pin. See layout guidelines in datasheet for more detailed information.
PD - 94336c
05/20/03
iP1001
www.irf.com
1
iP1001 Internal Block Diagram
V
FS
GNDS
SGND
PGND
V
SW
V
IN
V
F
& Driver
D4
PGOOD
DAC
V
DD
PWM
D0
D1
D2
D3
ENABLE
5 Bit
ILIM
FREQ
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| IP1001-DS-R01 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Integrated 10/100/1000 Gigabit Ethernet Transceiver |
| IP1001-DS-R02 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Integrated 10/100/1000 Gigabit Ethernet Transceiver |
| IP1001-DS-R03 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Integrated 10/100/1000 Gigabit Ethernet Transceiver |
| IP1001-DS-R04 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Integrated 10/100/1000 Gigabit Ethernet Transceiver |
| IP1001-DS-R05 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Integrated 10/100/1000 Gigabit Ethernet Transceiver |
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