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參數(shù)資料
| 型號(hào)： | IP1001 |
| 廠商： | International Rectifier |
| 英文描述： | Full Function Synchronous Buck Power Block |
| 中文描述： | 全功能的同步降壓電源模塊 |
| 文件頁(yè)數(shù)： | 13/18頁(yè) |
| 文件大?。?/td> | 507K |
| 代理商： | IP1001 |
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13
iP1001
For stable and noise free operation of the whole
power system it is recommended that the designer
uses to the following guidelines.
1.
Follow the layout scheme presented in Fig.9.
Make sure that the output inductor L1 is placed as
close to the iP1001 as possible to prevent noise
propagation that can be caused by switching of
power at the switching node V
SW
, to sensitive circuits.
2.
Provide a mid-layer solid ground with connections
to the top layer through vias. The two PGND pads of
the iP1001 also need to be connected to the same
ground plane through vias.
3.
Do not connect SGND pins of the iP1001 to PGND.
4.
To increase power supply noise immunity, place
input and output capacitors close to one another, as
shown in the layout diagram. This will provide short
high current paths that are essential at the ground
terminals.
Fig 9.
iP1001 suggested layout
5.
Although there is a certain degree of V
IN
bypassing inside the iP1001, the external input
decoupling capacitors should be as close to the
device as possible.
6.
In situations where the load is located at an
appreciable distance from the iP1001 block, it is
recommended that at least one or two capacitors
be placed close to the iP1001 to derive the V
F
signal.
7.
The V
connection to the output capacitors should
be as short as possible and should be routed as
far away from noise generating traces as possible.
8.
V
& GNDS pins need to be connected at the
load for remote sensing. If remote sensing is not
used connect V
FS
to V
F
and GNDS to PGND.
9.
Refer to IR application note AN-1029 to determine
what size vias and what copper weight and
thickness to use when designing the PCB.
Layout Guidelines
Input
Terminal
Load
Terminal
V
OUT
Output Caps (C
OUT
)
Input Caps (C
IN
)
V
IN
PGND
V
SW
Output Inductor (L
1
)
PGND
iP1001 Block
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