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參數(shù)資料
| 型號： | INT5130CS |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Integrated Powerline MAC/PHY Transceiver |
| 中文描述： | 綜合電力線MAC /物理層收發(fā)器 |
| 文件頁數(shù)： | 7/38頁 |
| 文件大小： | 1352K |
| 代理商： | INT5130CS |
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INTELLON CONFIDENTIAL
Rev 8.1
7
ADVANCE INFORMATION
INT5130 Integrated Powerline MAC /PHY Transceiver Technical Data Sheet
SPI Master Port (Configuration PROM Interface)
SPI_DO
Output
SPI Master Data Out
INT5130 configuration data from the INT5130 to the
external E
2
PROM.
SPI Master Data In
INT5130 configuration data from the external
E
2
PROM to the INT5130.
SPI Master Clock
Timing reference signal for SPI_DI and SPI_DO.
SPI Master Chip Select
Enables data transfers on the SPI Master Interface.
SPI_DI
Input
SPI_CLK
Output
SPI_CS
Output
LED Control
LED0_N
Output
LED0_N: Collision Detection
Activate for a duration of 10 ms upon detection of a
collision.
LED1_N: Activity Detection
Activate for a duration of 10 ms upon the receipt of
a properly addressed unicast or broadcast frame or
the transmission of a frame.
LED2_N: Link Detection
Turns on when initialization is complete successfully
and “network” is established.
LED1_N
Output
LED2_N
Output
Analog Front End Interface
ADC_CLK
Output
ADC Clock
ADC clock output to the INT1000 Analog Conversion
IC.
DAC Clock
DAC clock output to the INT1000 Analog Conversion
IC.
Analog Front End Transmit Enable
Transmit Enable signal
Analog Front End Receive Enable
Receive Enable signal
Analog/Digital I/O
ADC and DAC Data. Multiplexed parallel interface to
INT1000 Analog Conversion IC.
AGC Gain Select
Gain control driven by the INT5130 to set the AGC
level.
ADC Calibrate
This pin must remain low during normal operation of
the ADC. It is pulsed high to request a calibration
cycle. The ADC_CAL minimum pulse width is 4
clock cycles. While this signal is high the ADC
calibration registers are cleared and the calibration
control circuitry is reset. The ADC_CAL pulse will
go high 217 clock cycles (2.6 ms) after power on
reset drops, and will remain high for the required 4
clock cycles.
DAC_CLK
Output
TX_EN
Output
RX_EN
Output
ADIO[9:0]
Input/Output
AGC[7:0]
Output
ADC_CAL
Output
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