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參數(shù)資料
| 型號： | INT5130CS |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Integrated Powerline MAC/PHY Transceiver |
| 中文描述： | 綜合電力線MAC /物理層收發(fā)器 |
| 文件頁數(shù)： | 6/38頁 |
| 文件大小： | 1352K |
| 代理商： | INT5130CS |
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INTELLON CONFIDENTIAL
Rev 8.1
6
ADVANCE INFORMATION
INT5130 Integrated Powerline MAC /PHY Transceiver Technical Data Sheet
General Purpose Serial Interface (GPSI)
These pins are multiplexed with the MII pins and are selected when MII_GSPI_N signal is at VSS.
GPSI_RXD
Output
GPSI Receive Data
This signal carries data received from the powerline
and delivers to the external host. Data is driven on
the falling edge of the GPSI_RXCLK.
GPSI Receive Clock
This signal is the timing reference for the serial data
transfer from the INT5130 to the external host. This
clock operates at 10 MHz.
GPSI Transmit Data
This signal carries data transmitted from the external
host to the INT5130 for transmission over the
powerline. Data is latched on the falling edge of the
GPSI_TXCLK.
GPSI Transmit Clock
This signal is the timing reference for the serial data
transfer from the external host to the INT5130. This
clock operates at 10 MHz.
GPSI Receive Enable
Indicates valid data is on the GPSI_RXD line.
GPSI Transmit Enable
Indicates when the external host is providing valid
data on GPSI_TXD.
GPSI Transmit Busy
The GPSI Transmit Busy signal is asserted within
120 GPSI clocks after GPSI_TXEN indicates a TX
frame is being sent by the local host. GPSI_TXBSY
stays true until the entire TX frame is loaded into an
internal buffer AND a new buffer is allocated to the
GPSI TX interface. This signal should be monitored
by the GPSI TX host. A new GPSI TX frame should
not be sent until GPSI_TXBSY returns to false to
prevent TX buffer overflows.
GPSI_TXBSY is an asynchronous output signal.
GPSI Collision Detect
This signal is driven false in GPSI mode.
GPSI_RXCLK
Output
GPSI_TXD
Input
GPSI_TXCLK
Output
GPSI_RXEN
Output
GPSI_TXEN
Input
GPSI_TXBSY
Output
GPSI_COL
Output
SPI Slave Port
Selected when MDI_SPIS_N signal is at VSS.
SPIS_SDO
Output
SPI Slave Data Out
SPI data from the INT5130 to the external host.
SPI Slave Data In
SPI data from the external host to the INT5130.
This pin is shared with the MDI_ADRSEL[1].
SPI Slave Clock
Timing reference signal for SPI_SDI and SPI_SDO.
SPI Slave Chip Select
Enables SPI data transfers on the INT5130. This
pin is shared with the MDI_ADRSEL[0].
SPIS_SDI
Input
SPIS_SCLK
Input
SPIS_CS_N
Input
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