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參數(shù)資料
| 型號： | IDT82V3202NLG |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 31/117頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PLL WAN EBU SGL 68-VFQFPN |
| 標準包裝： | 21 |
| 類型： | 時鐘/頻率發(fā)生器，多路復用器 |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，SONET/SDH，Stratum |
| 輸入： | CMOS |
| 輸出： | CMOS，LVDS，PECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:2 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 622.08MHz |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 68-VFQFN 裸露焊盤 |
| 供應商設備封裝： | 68-VFQFPN（10x10） |
| 包裝： | 托盤 |
| 其它名稱： | 82V3202NLG |
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IDT82V3202
EBU WAN PLL
Functional Description
20
September 11, 2009
3.4
INPUT CLOCK PRE-DIVIDER
Each input clock is assigned an internal Pre-Divider. The Pre-Divider
is used to divide the clock frequency down to the DPLL required fre-
quency, which is no more than 38.88 MHz. For each input clock, the
DPLL required frequency is set by the corresponding IN_FREQ[3:0] bits.
If the input clock is of 2 kHz, 4 kHz or 8 kHz, the Pre-Divider is
bypassed automatically and the corresponding IN_FREQ[3:0] bits
should be set to match the input frequency; the input clock can be
inverted, as determined by the IN_2K_4K_8K_INV bit.
Each Pre-Divider consists of a DivN Divider and a Lock 8k Divider, as
shown in Figure 4.
Either the DivN Divider or the Lock 8k Divider can be used or both
can be bypassed, as determined by the DIRECT_DIV bit and the
LOCK_8K bit.
When the DivN Divider is used, the division factor setting should
observe the following order:
1. Select an input clock by the PRE_DIV_CH_VALUE[3:0] bits;
2. Write the lower eight bits of the division factor to the
PRE_DIVN_VALUE[7:0] bits;
3. Write the higher eight bits of the division factor to the
PRE_DIVN_VALUE[14:8] bits.
Once the division factor is set for the input clock selected by the
PRE_DIV_CH_VALUE[3:0] bits, it is valid until a different division factor
is set for the same input clock. The division factor is calculated as fol-
lows:
Division Factor = (the frequency of the clock input to the DivN
Divider ÷ the frequency of the DPLL required clock set by the
IN_FREQ[3:0] bits) - 1
The DivN Divider can only divide the input clock whose frequency is
lower than (
<) 155.52 MHz.
When the Lock 8k Divider is used, the input clock is divided down to
8 kHz automatically.
The Pre-Divider configuration and the division factor setting depend
on the input clock on one of the clock input pin and the DPLL required
clock. Here is an example:
The input clock on the IN2_CMOS pin is 155.52 MHz; the DPLL
required clock is 6.48 MHz by programming the IN_FREQ[3:0] bits of
register IN2_CMOS_CNFG to ‘0010’. Do the following to divide the input
clock:
Use the DivN Divider to divide the clock down to 6.48 MHz:
Set the PRE_DIV_CH_VALUE[3:0] bits to ‘0011’;
Set the DIRECT_DIV bit in Register IN2_CMOS_CNFG to ‘1’
and the LOCK_8K bit in Register IN2_CMOS_CNFG to ‘0’;
155.52 ÷ 6.48 = 24; 24 - 1 = 23, so set the
PRE_DIVN_VALUE[14:0] bits to ‘10111’.
Figure 4. Pre-Divider for An Input Clock
Table 4: Related Bit / Register in Chapter 3.4
Bit
Register
Address (Hex)
IN_FREQ[3:0]
IN1_CMOS_CNFG, IN2_CMOS_CNFG
16, 17
DIRECT_DIV
LOCK_8K
IN_2K_4K_8K_INV
FR_SYNC_CNFG
74
PRE_DIV_CH_VALUE[3:0]
PRE_DIV_CH_CNFG
23
PRE_DIVN_VALUE[14:0]
PRE_DIVN[14:8]_CNFG, PRE_DIVN[7:0]_CNFG
25, 24
input clock
DivN Divider
Lock 8k Divider
Pre-Divider
DIRECT_DIV bit
LOCK_8K bit
DPLL required clock
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| IDT82V3202NLG8 | 功能描述:IC PLL WAN EBU SGL 68-VFQFPN RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標準包裝:1,500 系列:- 類型:時鐘緩沖器/驅動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應商設備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| IDT82V3202NLGBLANK | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:EBU WAN PLL |
| IDT82V3255 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:WAN PLL |
| IDT82V3255_08 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:WAN PLL |
| IDT82V3255DK | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:WAN PLL |
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