參數(shù)資料
型號: IDT82V3202NLG
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 29/117頁
文件大?。?/td> 0K
描述: IC PLL WAN EBU SGL 68-VFQFPN
標準包裝: 21
類型: 時鐘/頻率發(fā)生器,多路復用器
PLL:
主要目的: 以太網(wǎng),SONET/SDH,Stratum
輸入: CMOS
輸出: CMOS,LVDS,PECL
電路數(shù): 1
比率 - 輸入:輸出: 2:2
差分 - 輸入:輸出: 無/是
頻率 - 最大: 622.08MHz
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 68-VFQFN 裸露焊盤
供應商設備封裝: 68-VFQFPN(10x10)
包裝: 托盤
其它名稱: 82V3202NLG
IDT82V3202
EBU WAN PLL
Functional Description
19
September 11, 2009
3.3
INPUT CLOCKS & FRAME SYNC SIGNALS
Altogether two clocks and two frame sync signals are input to the
device.
3.3.1
INPUT CLOCKS
The device provides two CMOS input clock ports: IN1_CMOS and
IN2_CMOS.
According to the input clock source, the following clock sources are
supported:
T1: Recovered clock from STM-N or OC-n
T2: PDH network synchronization timing
T3: External synchronization reference timing
The clock sources can be from T1, T2 or T3.
For SDH and SONET networks, the default frequency is different.
SONET / SDH frequency selection is controlled by the IN_SONET_SDH
bit. During reset, the default value of the IN_SONET_SDH bit is deter-
mined by the SONET/SDH pin: high for SONET and low for SDH. After
reset, the input signal on the SONET/SDH pin takes no effect.
3.3.2
FRAME SYNC INPUT SIGNALS
Two 2 kHz, 4 kHz or 8 kHz frame sync signals are input on the
EX_SYNC1 and EX_SYNC2 pins respectively. They are CMOS inputs.
The input frequency should match the setting in the SYNC_FREQ[1:0]
bits. The frame sync signals are only valid for the OC-n clock (6.48 MHz,
19.44 MHz, 38.88 MHz and 77.76 MHz) input.
Only one of the two frame sync input signals is used for frame sync
output signal synchronization. Refer to Chapter 3.13.2 Frame SYNC
Output Signal for details.
Table 3: Related Bit / Register in Chapter 3.3
Bit
Register
Address (Hex)
IN_SONET_SDH
INPUT_MODE_CNFG
09
SYNC_FREQ[1:0]
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