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| 型號： | HYS64T16000HDL-2.5-A |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 元件分類： | DRAM |
| 英文描述： | 16M X 64 DDR DRAM MODULE, 0.4 ns, DMA200 |
| 封裝： | GREEN, SODIMM-200 |
| 文件頁數(shù)： | 45/46頁 |
| 文件大?。?/td> | 833K |
| 代理商： | HYS64T16000HDL-2.5-A |
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HYS64T[16/32/64]0xxxHDL–[2.5/3.7/5]–A
Small Outline DDR2 SDRAM Modules
Pin Configuration and Block Diagrams
Data Sheet
5
Rev. 1.1, 2005-06
02182004-HWZ1-64OM
2
Pin Configuration and Block Diagrams
2.1
Pin Configuration
The pin configuration of the Small Outline DDR2 SDRAM DIMM is listed by function in Table 6 (200 pins). The
abbreviations used in columns Pin and Buffer Type are explained in Table 7 and Table 8 respectively. The pin
numbering is depicted in Figure 1
Table 6
Pin Configuration of SO-DIMM
Pin or Ball No.
Name
Pin
Type
Buffer
Type
Function
Clock Signals
30
CK0
I
SSTL
Clock Signals 2:0, Complement Clock Signals 2:0
The system clock inputs. All address and command
lines are sampled on the cross point of the rising edge
of CK and the falling edge of CK. A Delay Locked
Loop (DLL) circuit is driven from the clock inputs and
output timing for read operations is synchronized to
the input clock.
164
CK1
I
SSTL
32
CK0
I
SSTL
166
CK1
I
SSTL
79
CKE0
I
SSTL
Clock Enable Rank 1:0
Activates the DDR2 SDRAM CK signal when HIGH
and deactivates the CK signal when LOW. By
deactivating the clocks, CKE LOW initiates the Power
Down Mode or the Self Refresh Mode.
Note: 2 Ranks module
80
CKE1
I
SSTL
NC
—
Not Connected
Note: 1-rank module
Control Signals
110
S0
I
SSTL
Chip Select Rank 1:0
Enables the associated DDR2 SDRAM command
decoder when LOW and disables the command
decoder when HIGH. When the command decoder is
disabled, new commands are ignored but previous
operations continue. Rank 0 is selected by S0; Rank
1 is selected by S1. Ranks are also called "Physical
banks".2 Ranks module
115
S1
I
SSTL
NC
—
Not Connected
Note: 1-rank module
108
RAS
I
SSTL
Row Address Strobe
When sampled at the cross point of the rising edge of
CK,and falling edge of CK, RAS, CAS and WE define
the operation to be executed by the SDRAM.
113
CAS
I
SSTL
Column Address Strobe
109
WE
I
SSTL
Write Enable
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