參數(shù)資料
型號(hào): HYS64T16000HDL-2.5-A
廠商: INFINEON TECHNOLOGIES AG
元件分類: DRAM
英文描述: 16M X 64 DDR DRAM MODULE, 0.4 ns, DMA200
封裝: GREEN, SODIMM-200
文件頁數(shù): 27/46頁
文件大?。?/td> 833K
代理商: HYS64T16000HDL-2.5-A
Data Sheet
30
Rev. 1.1, 2005-06
02182004-HWZ1-64OM
HYS64T[16/32/64]0xxxHDL–[2.5/3.7/5]–A
Small Outline DDR2 SDRAM Modules
Electrical Characteristics
3.4.1
I
DD Test Conditions
For testing the
I
DD parameters, the timing parameters as in Table 24 are used.
3.4.2
On Die Termination (ODT) Current
The ODT function adds additional current consumption
to the DDR2 SDRAM when enabled by the EMRS(1).
Depending on address bits A[6,2] in the EMRS(1) a
“weak” or “strong” termination can be selected. The
current consumption for any terminated input pin,
depends on the input pin is in tri-state or driving 0 or 1,
as long a ODT is enabled during a given period of time.
Note: For power consumption calculations the ODT duty cycle has to be taken into account
Table 24
I
DD Measurement Test Conditions for DDR2–400 and DDR2–533
Parameter
Symbol
–3.7
–5
Unit
DDR2–533C
DDR2–400B
CAS Latency
CL
(IDD)
43
t
CK
Clock Cycle Time
t
CK(IDD)
3.75
5
ns
Active to Read or Write delay
t
RCD(IDD)
15
ns
Active to Active / Auto-Refresh command period
t
RC(IDD)
60
55
ns
Active bank A to Active bank B command delay
×81)
1)
×4 & ×8 (1 kB page size)
t
RRD(IDD)
7.5
ns
×162)
2)
×16 (2 kB page size), not on 256M components
t
RRD(IDD)
10
ns
Active to Precharge Command
t
RAS.MIN(IDD)
45
40
ns
t
RAS.MAX(IDD)
70000
ns
Precharge Command Period
t
RP(IDD)
15
ns
Average periodic Refresh interval
t
REFI
7.8
s
Table 25
ODT current per terminated pin
Parameter
Symbol Min.
Typ.
Max. Unit
EMRS(1) State
Enabled ODT current per DQ
ODT is HIGH; Data Bus inputs are FLOATING
I
ODTO
5
6
7.5
mA/DQ A6 = 0, A2 = 1
2.5
3
3.75
mA/DQ A6 = 1, A2 = 0
7.5
9
11.25 mA/DQ A6 = 1, A2 = 1
Active ODT current per DQ
ODT is HIGH; worst case of Data Bus inputs are
STABLE or SWITCHING.
I
ODTT
10
12
15
mA/DQ A6 = 0, A2 = 1
5
6
7.5
mA/DQ A6 = 1, A2 = 0
15
18
22.5
mA/DQ A6 = 1, A2 = 0
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