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參數(shù)資料
| 型號： | HM5212805F |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 128M LVTTL interface SDRAM(128M LVTTL 接口同步DRAM) |
| 中文描述： | 128M的LVTTL接口的SDRAM（128M的LVTTL接口同步的DRAM） |
| 文件頁數(shù)： | 22/63頁 |
| 文件大?。?/td> | 858K |
| 代理商： | HM5212805F |
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HM5212165F/HM5212805F-75/A60/B60
22
2. Single write:
A single write operation is enabled by setting OPCODE (A9, A8) to (1, 0). In a single write
operation, data is only written to the column address (AY0 to AY8; HM5212165F, AY0 to AY9;
HM5212805F) and the bank select address (A12/A13) specified by the write command set cycle without
regard to the burst length setting. (The latency of data input is 0 clock).
WRIT
CLK
Command
Din
ACTV
Row
Column
in 0
Address
t
RCD
Auto Precharge
Read with auto-precharge:
In this operation, since precharge is automatically performed after completing a
read operation, a precharge command need not be executed after each read operation. The command executed
for the same bank after the execution of this command must be the bank active (ACTV) command. In
addition, an interval defined by l
APR
is required before execution of the next command.
CAS
latency
Precharge start cycle
3
2 cycle before the final data is output
2
1 cycle before the final data is output
Burst Read
(Burst Length = 4)
CLK
lAPR
lRAS
lAPR
CL=2 Command
CL=3 Command
DQ (input)
DQ (input)
Note: Internal auto-precharge starts at the timing indicated by " ".
And an interval of t
RAS
(l
RAS
) is required between previous active (ACTV) command and internal precharge " ".
ACTV
READ A
ACTV
out3
out2
out1
out0
lRAS
ACTV
READ A
ACTV
out3
out2
out1
out0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HM5212165F | 128M LVTTL interface SDRAM(128M LVTTL 接口同步DRAM) |
| HM5225165BTT-75 | 256M LVTTL interface SDRAM 133 MHz/100 MHz 4-Mword 】 16-bit 】 4-bank/8-Mword 】 8-bit 】 4-bank /16-Mword 】 4-bit 】 4-bank PC/133, PC/100 SDRAM |
| HM5225805BLTT-A6 | 256M LVTTL interface SDRAM 133 MHz/100 MHz 4-Mword 】 16-bit 】 4-bank/8-Mword 】 8-bit 】 4-bank /16-Mword 】 4-bit 】 4-bank PC/133, PC/100 SDRAM |
| HM5225405B-B6 | 256M LVTTL interface SDRAM 133 MHz/100 MHz 4-Mword 】 16-bit 】 4-bank/8-Mword 】 8-bit 】 4-bank /16-Mword 】 4-bit 】 4-bank PC/133, PC/100 SDRAM |
| HM5225405BLTT-75 | POT 20K OHM 9MM HORZ NO BUSHING |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HM5212805FLTD-75 | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M LVTTL interface SDRAM 133 MHz/100 MHz 2-Mword × 16-bit × 4-bank/4-Mword × 8-bit × 4-bank PC/133, PC/100 SDRAM |
| HM5212805FLTD-A60 | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:128M LVTTL interface SDRAM 133 MHz/100 MHz 2-Mword X 16-bit X 4-bank/4-Mword X 8-bit X 4-bank PC/133, PC/100 SDRAM |
| HM5212805FLTD-B60 | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:128M LVTTL interface SDRAM 133 MHz/100 MHz 2-Mword X 16-bit X 4-bank/4-Mword X 8-bit X 4-bank PC/133, PC/100 SDRAM |
| HM5212805FTD-75 | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M LVTTL interface SDRAM 133 MHz/100 MHz 2-Mword × 16-bit × 4-bank/4-Mword × 8-bit × 4-bank PC/133, PC/100 SDRAM |
| HM5212805FTD-A60 | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:128M LVTTL interface SDRAM 133 MHz/100 MHz 2-Mword X 16-bit X 4-bank/4-Mword X 8-bit X 4-bank PC/133, PC/100 SDRAM |
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