參數(shù)資料
型號(hào)： HM5212805F
廠商： Hitachi,Ltd.
英文描述： 128M LVTTL interface SDRAM(128M LVTTL 接口同步DRAM)
中文描述： 128M的LVTTL接口的SDRAM（128M的LVTTL接口同步的DRAM）
文件頁(yè)數(shù)： 10/63頁(yè)
文件大?。?/td> 858K
代理商： HM5212805F
HM5212165F/HM5212805F-75/A60/B60
10
DQM Truth Table
(HM5212165F)
CKE
Command
Symbol
n - 1
n
DQMU
DQML
Upper byte (DQ8 to DQ15) write enable/output enable ENBU
H
×
×
×
×
L
×
Lower byte (DQ0 to DQ7) write enable/output enable
ENBL
H
×
L
Upper byte (DQ8 to DQ15) write inhibit/output disable MASKU
H
H
×
Lower byte (DQ0 to DQ7) write inhibit/output disable
Note:
H: V
IH
. L: V
IL
.
×
: V
IH
or V
IL
.
Write: I
DID
is needed.
Read: I
DOD
is needed.
MASKL
H
×
H
DQM Truth Table
(HM5212805F)
CKE
Command
Symbol
n - 1
n
DQM
Write enable/output enable
ENB
H
×
×
L
Write inhibit/output disable
Note:
H: V
IH
. L: V
IL
.
×
: V
IH
or V
IL
.
Write: I
DID
is needed.
Read: I
DOD
is needed.
MASK
H
H
The SDRAM can mask input/output data by means of DQM, DQMU/DQML. DQMU masks the upper byte
and DQML masks the lower byte (HM5212165F).
During reading, the output buffer is set to Low-Z by setting DQM, DQMU/DQML to Low, enabling data
output. On the other hand, when DQM, DQMU/DQML is set to High, the output buffer becomes High-Z,
disabling data output.
During writing, data is written by setting DQM, DQMU/DQML to Low. When DQM, DQMU/DQML is set
to High, the previous data is held (the new data is not written). Desired data can be masked during burst read
or burst write by setting DQM, DQMU/DQML. For details, refer to the DQM, DQMU/DQML control
section of the SDRAM operating instructions.
相關(guān)PDF資料
PDF描述
HM5212165F 128M LVTTL interface SDRAM(128M LVTTL 接口同步DRAM)
HM5225165BTT-75 256M LVTTL interface SDRAM 133 MHz/100 MHz 4-Mword 】 16-bit 】 4-bank/8-Mword 】 8-bit 】 4-bank /16-Mword 】 4-bit 】 4-bank PC/133, PC/100 SDRAM
HM5225805BLTT-A6 256M LVTTL interface SDRAM 133 MHz/100 MHz 4-Mword 】 16-bit 】 4-bank/8-Mword 】 8-bit 】 4-bank /16-Mword 】 4-bit 】 4-bank PC/133, PC/100 SDRAM
HM5225405B-B6 256M LVTTL interface SDRAM 133 MHz/100 MHz 4-Mword 】 16-bit 】 4-bank/8-Mword 】 8-bit 】 4-bank /16-Mword 】 4-bit 】 4-bank PC/133, PC/100 SDRAM
HM5225405BLTT-75 POT 20K OHM 9MM HORZ NO BUSHING
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HM5212805FLTD-75 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M LVTTL interface SDRAM 133 MHz/100 MHz 2-Mword × 16-bit × 4-bank/4-Mword × 8-bit × 4-bank PC/133, PC/100 SDRAM
HM5212805FLTD-A60 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:128M LVTTL interface SDRAM 133 MHz/100 MHz 2-Mword X 16-bit X 4-bank/4-Mword X 8-bit X 4-bank PC/133, PC/100 SDRAM
HM5212805FLTD-B60 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:128M LVTTL interface SDRAM 133 MHz/100 MHz 2-Mword X 16-bit X 4-bank/4-Mword X 8-bit X 4-bank PC/133, PC/100 SDRAM
HM5212805FTD-75 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M LVTTL interface SDRAM 133 MHz/100 MHz 2-Mword × 16-bit × 4-bank/4-Mword × 8-bit × 4-bank PC/133, PC/100 SDRAM
HM5212805FTD-A60 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:128M LVTTL interface SDRAM 133 MHz/100 MHz 2-Mword X 16-bit X 4-bank/4-Mword X 8-bit X 4-bank PC/133, PC/100 SDRAM
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