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參數資料
| 型號： | HM5212805F |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 128M LVTTL interface SDRAM(128M LVTTL 接口同步DRAM) |
| 中文描述： | 128M的LVTTL接口的SDRAM（128M的LVTTL接口同步的DRAM） |
| 文件頁數： | 15/63頁 |
| 文件大小： | 858K |
| 代理商： | HM5212805F |
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HM5212165F/HM5212805F-75/A60/B60
15
From PRECHARGE state, command operation
To [DESL], [NOP] or [BST]:
When these commands are executed, the SDRAM enters the IDLE state after
t
RP
has elapsed from the completion of precharge.
From IDLE state, command operation
To [DESL], [NOP], [BST], [PRE] or [PALL]:
These commands result in no operation.
To [ACTV]:
The bank specified by the address pins and the ROW address is activated.
To [REF], [SELF]:
The SDRAM enters refresh mode (auto-refresh or self-refresh).
To [MRS]:
The SDRAM enters the mode register set cycle.
From ROW ACTIVE state, command operation
To [DESL], [NOP] or [BST]:
These commands result in no operation.
To [READ], [READ A]:
A read operation starts. (However, an interval of t
RCD
is required.)
To [WRIT], [WRIT A]:
A write operation starts. (However, an interval of t
RCD
is required.)
To [ACTV]:
This command makes the other bank active. (However, an interval of t
RRD
is required.)
Attempting to make the currently active bank active results in an illegal command.
To [PRE], [PALL]:
These commands set the SDRAM to precharge mode. (However, an interval of t
RAS
is
required.)
From READ state, command operation
To [DESL], [NOP]:
These commands continue read operations until the burst operation is completed.
To [BST]:
This command stops a full-page burst.
To [READ], [READ A]:
Data output by the previous read command continues to be output. After
CAS
latency, the data output resulting from the next command will start.
To [WRIT], [WRIT A]:
These commands stop a burst read, and start a write cycle.
To [ACTV]:
This command makes other banks bank active. (However, an interval of t
RRD
is required.)
Attempting to make the currently active bank active results in an illegal command.
To [PRE], [PALL]:
These commands stop a burst read, and the SDRAM enters precharge mode.
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PDF描述 |
|---|---|
| HM5212165F | 128M LVTTL interface SDRAM(128M LVTTL 接口同步DRAM) |
| HM5225165BTT-75 | 256M LVTTL interface SDRAM 133 MHz/100 MHz 4-Mword 】 16-bit 】 4-bank/8-Mword 】 8-bit 】 4-bank /16-Mword 】 4-bit 】 4-bank PC/133, PC/100 SDRAM |
| HM5225805BLTT-A6 | 256M LVTTL interface SDRAM 133 MHz/100 MHz 4-Mword 】 16-bit 】 4-bank/8-Mword 】 8-bit 】 4-bank /16-Mword 】 4-bit 】 4-bank PC/133, PC/100 SDRAM |
| HM5225405B-B6 | 256M LVTTL interface SDRAM 133 MHz/100 MHz 4-Mword 】 16-bit 】 4-bank/8-Mword 】 8-bit 】 4-bank /16-Mword 】 4-bit 】 4-bank PC/133, PC/100 SDRAM |
| HM5225405BLTT-75 | POT 20K OHM 9MM HORZ NO BUSHING |
相關代理商/技術參數 |
參數描述 |
|---|---|
| HM5212805FLTD-75 | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M LVTTL interface SDRAM 133 MHz/100 MHz 2-Mword × 16-bit × 4-bank/4-Mword × 8-bit × 4-bank PC/133, PC/100 SDRAM |
| HM5212805FLTD-A60 | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:128M LVTTL interface SDRAM 133 MHz/100 MHz 2-Mword X 16-bit X 4-bank/4-Mword X 8-bit X 4-bank PC/133, PC/100 SDRAM |
| HM5212805FLTD-B60 | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:128M LVTTL interface SDRAM 133 MHz/100 MHz 2-Mword X 16-bit X 4-bank/4-Mword X 8-bit X 4-bank PC/133, PC/100 SDRAM |
| HM5212805FTD-75 | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M LVTTL interface SDRAM 133 MHz/100 MHz 2-Mword × 16-bit × 4-bank/4-Mword × 8-bit × 4-bank PC/133, PC/100 SDRAM |
| HM5212805FTD-A60 | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:128M LVTTL interface SDRAM 133 MHz/100 MHz 2-Mword X 16-bit X 4-bank/4-Mword X 8-bit X 4-bank PC/133, PC/100 SDRAM |
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