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參數(shù)資料
| 型號： | HM51S4265DTT-6 |
| 元件分類： | DRAM |
| 英文描述： | 256K X 16 EDO DRAM, 60 ns, PDSO40 |
| 封裝： | 0.400 INCH, PLASTIC, MO-133BA, TSOP2-44/40 |
| 文件頁數(shù)： | 6/33頁 |
| 文件大?。?/td> | 331K |
| 代理商： | HM51S4265DTT-6 |
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HM514265D Series, HM51S4265D Series
14
11. These parameters are referred to
CAS leading edge in an early write cycle and to WE leading
edge in a delayed write or a read-modify-write cycle.
12. t
RASC defines RAS pulse width in EDO page mode cycles.
13. Access time is determined by the longest among t
AA, t CAC and t ACP.
14. An initial pause of 100
s is required after power up followed by a minimum of eight initialization
cycles (
RAS-only refresh cycle or CAS-before-RAS refresh cycle). If the internal refresh counter
is used, a minimum of eight
CAS-before-RAS refresh cycles is required.
15. In delayed write or read-modify-write cycles,
OE must disable output buffer prior to applying data
to the device.
16. Either t
RCH or tRRH must be satisfied for a read cycle.
17. When both
UCAS and LCAS go low at the same time, all 16-bit data are written into the device.
UCAS and LCAS cannot be staggered within the same write/read cycles.
18. All the V
CC and VSS pins shall be supplied with the same voltages.
19. t
ASC, tCAH, t RCS, t WCS, t WCH, t CSR and t RPC are determined by the earlier falling edge of UCAS or LCAS .
20. t
CRP, t CHR, t ACP, tRCH and t CPW are determined by the later rising edge of UCAS or LCAS .
21. t
CWL, tDH, tDS and t CHS should be satisfied by both UCAS and LCAS .
22. t
CPN and t CP are determined by the time that both UCAS and LCAS are high.
23. When output buffers are enabled once, sustain the low impedance state until valid data is
obtained. When output buffer is turned on and off within a very short time, generally it causes
large V
CC/VSS line noise, which causes to degrade VIH min/VIL max
level.
24. t
HPC (min) can be achieved during a series of EDO page mode early write cycles or EDO page
mode read cycles. If both write and read operation are mixed in a EDO page mode
RAS cycle
(EDO page mode mix cycle (1), (2)), minimum value of
CAS cycle t
HPC (tCAS + tCP + 2tT) becomes
greater than the specified t
HPC (min) value.
25. Data output turns off and becomes high impedance from later rising edge of
RAS and CAS.
Hold time and turn off time are specified by the timing specifications of later rising edge of
RAS
and
CAS between t
OHR and tOH and between tOFR and t OFF1.
26. t
DOH defines the time at which the output level satisfies the output timing reference levels.
Measured with the test conditions.
27. t
RAS (min) = tRWD (min) + tRWL (min) + tT in read-modify-write cycle.
28. t
CAS (min) = tCWD (min) + tCWL (min) + tT in read-modify-write cycle.
29. t
CSH (min) can be achieved when tRCD ≤ tCSH (min) – tCAS (min).
30. Please do not use t
RASS timing, 10 s ≤ tRASS ≤ 100 s.
During this period, the device is in
transition state from normal operation mode to self refresh mode. If t
RASS > 100 s, then RAS
precharge time should use t
RPS instead of tRP.
31. If you use distributed CBR refresh mode with 15.6
s interval in normal read/write cycle, CBR
refresh should be executed within 15.6
s immediately after exiting from and before entering into
self refresh mode.
32. If you use
RAS only refresh or CBR burst refresh mode in normal read/write cycle, 512 cycles of
distributed CBR refresh with 15.6
s interval should be executed within 8 ms immediately after
exiting from and before entering into the self refresh mode.
33. Repetitive self refresh mode without refreshing all memory is not allowed. Once you exit from
self refresh mode, all memory cells need to be refreshed before re-entering the self refresh mode
again.
34. XXX: H or L (H: V
IH (min) ≤ VIN ≤ VIH (max), L: VIL (min) ≤ VIN ≤ VIL (max))
///////: Invalid Dout
When the address, clock and input pins are not described on timing waveforms, their pins must
be applied V
IH or VIL.
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