參數(shù)資料
型號(hào): HM51S4265DTT-6
元件分類: DRAM
英文描述: 256K X 16 EDO DRAM, 60 ns, PDSO40
封裝: 0.400 INCH, PLASTIC, MO-133BA, TSOP2-44/40
文件頁數(shù): 32/33頁
文件大?。?/td> 331K
代理商: HM51S4265DTT-6
HM514265D Series, HM51S4265D Series
8
3. Address can be changed once or less within one EDO page cycle.
4. V
IH ≥ VCC – 0.2 V, 0 ≤ VIL ≤ 0.2 V, Address can be changed once or less while RAS = VIL.
5. All the V
CC pins should be supplied with the same voltage.
And all the V
SS pins should be
supplied with the same voltage.
Capacitance (Ta = +25
°C, V
CC = 5 V ±5%) (HM51(S)4265D-5/6R)
(Ta = +25
°C, V
CC = 5 V ±10%) (HM51(S)4265D-6/7/8)
Parameter
Symbol
Typ
Max
Unit
Notes
Input capacitance (Address)
C
I1
5
pF
1
Input capacitance (Clocks)
C
I2
7
pF
1
Output capacitance (Data-in, Data-out)
C
I/O
10
pF
1, 2
Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2.
RAS, UCAS and LCAS = V
IH to disable Dout.
AC Characteristics
(Ta = 0 to 70
°C, V
CC = 5 V ±5%, VSS = 0 V) (HM51(S)4265D-5/6R) *
1, *14, *15, *17, *18
(Ta = 0 to +70
°C, V
CC = 5 V ±10%, VSS = 0 V)(HM51(S)4265D-6/7/8) *
1, *14, *15, *17, *18
Test Conditions
Input rise and fall time: 2 ns
Input levels: V
IL = 0 V, VIH = 3.0 V
Input timing reference levels: 0.8 V, 2.4 V
Output timing reference levels: 0.8 V, 2.0 V
Output load: 1 TTL gate + C
L (50 pF) (Including scope and jig)
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