參數(shù)資料
型號(hào)： HM51S4265DTT-6
元件分類： DRAM
英文描述： 256K X 16 EDO DRAM, 60 ns, PDSO40
封裝： 0.400 INCH, PLASTIC, MO-133BA, TSOP2-44/40
文件頁(yè)數(shù)： 29/33頁(yè)
文件大小： 331K
代理商： HM51S4265DTT-6
HM514265D Series, HM51S4265D Series
5
Operation Table
The HM51(S)4265D series has the following 11 operation modes.
1. Read cycle
2. Early write cycle
3. Delayed write cycle
4. Read-modify-write cycle
5. RAS-only refresh cycle
6. CAS-before-RAS refresh cycle
7. Self refresh cycle (HM51S4265D)
8. EDO page mode read cycle
9. EDO page mode early write cycle
10. EDO page mode delayed write cycle
11. EDO page mode read-modify-write cycle
Inputs
RAS
LCAS
UCAS
WE
OE
Output
Operation
H
D
Open
Standby
H
L
H
L
Valid
Standby
L
H
L
Valid
Read cycle
LL
L
L*
2
D
Open
Early write cycle
LL
L
L*
2
H
Undefined
Delayed write cycle
L
H to L
L to H
Valid
Read-modify-write cycle
L
H
D
Open
RAS-only refresh cycle
H to L
H
L
D
Open
CAS-before-RAS refresh cycle
L
H
Self refresh cycle (HM51S4265D)
LL
L
H to L
H
L
Valid
EDO page mode read cycle
L
H to L
L*
2
D
Open
EDO page mode early write cycle
L
H to L
L*
2
H
Undefined
EDO page mode delayed write cycle
L
H to L
L to H
Valid
EDO page mode read-modify-write cycle
L
H
Open
Read cycle (Output disabled)
Notes: 1. H: High(inactive) L: Low(active) D: H or L (H: V
IH (min) ≤ VIN ≤ VIH (max), L: VIL (min) ≤ VIN ≤ VIL
(max))
2. t
WCS ≥ 0 ns:
Early write cycle
t
WCS < 0 ns:
Delayed write cycle
3. Mode is determined by the OR function of the
UCAS and LCAS. (Mode is set by the earliest of
UCAS and LCAS active edge and reset by the latest of UCAS and LCAS inactive edge.)
However write operation and output High-Z control are done independently by each
UCAS,
LCAS.
ex. if
RAS = H to L, LCAS = L, UCAS = H, then CAS-before-RAS refresh cycle is selected.
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