參數(shù)資料
型號: HM51S4265DTT-6
元件分類: DRAM
英文描述: 256K X 16 EDO DRAM, 60 ns, PDSO40
封裝: 0.400 INCH, PLASTIC, MO-133BA, TSOP2-44/40
文件頁數(shù): 2/33頁
文件大小: 331K
代理商: HM51S4265DTT-6
HM514265D Series, HM51S4265D Series
10
Read Cycle
HM514265D, HM51S4265D
-5
-6/-6R
-7
-8
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Unit
Notes
Access time from
RAS
t
RAC
50
60
70
80
ns
2, 3
Access time from
CAS
t
CAC
15
15
20
20
ns
3, 4, 13
Access time from address t
AA
25
30
35
40
ns
3, 5, 13
Access time from
OE
t
OAC
15
15
20
20
ns
3, 23
Read command setup
time
t
RCS
0
0—
0
ns
19
Read command hold time
to
CAS
t
RCH
0
0
0
0
ns
16, 20
Read command hold time
to
RAS
t
RRH
0
0—
0
ns
16
Column address to
RAS lead time
t
RAL
25
30
35
40
ns
Column address to
CAS lead time
t
CAL
13
18
23
28
ns
Output buffer turn-off time t
OFF1
13
15
15
15
ns
6, 25
Output buffer turn-off time
to
OE
t
OFF2
13
15
15
15
ns
6
CAS to Din delay time
t
CDD
13
15
18
20
ns
RAS to Din delay time
t
RDD
13
15
18
20
ns
WE to Din delay time
t
WDD
13
15
18
20
ns
OE pulse width
t
OEP
13
15
20
20
ns
23
Turn-off to
RAS
t
OFR
13
15
15
15
ns
6, 25
Turn-off to
WE
t
WEZ
13
15
15
15
ns
6
Output data hold time
t
OH
5
5—
5
ns
25
Output data hold time
from
RAS
t
OHR
5
5—
5
ns
25
Read command hold time
from
RAS
t
RCHR
50
60
70
80
ns
Read command hold time
from
CAS
t
RCHC
15
15
18
20
ns
Read command hold time
from column address
t
RCHA
25
30
35
40
ns
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