- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄383036 > GS8170S18 (GSI TECHNOLOGY) 16Mb（1M x 18Bit）Synchronous SRAM(16M位（1M x 18位）同步靜態(tài)RAM) PDF資料下載
參數(shù)資料
| 型號： | GS8170S18 |
| 廠商： | GSI TECHNOLOGY |
| 英文描述： | 16Mb（1M x 18Bit）Synchronous SRAM(16M位（1M x 18位）同步靜態(tài)RAM) |
| 中文描述： | 16Mb的（100萬x 18位）同步SRAM（1,600位（100萬× 18位）同步靜態(tài)內(nèi)存） |
| 文件頁數(shù)： | 13/38頁 |
| 文件大小： | 934K |
| 代理商： | GS8170S18 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁當前第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁
Rev: 1.01 11/2000
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
13/38
2000, Giga Semiconductor, Inc.
A
Advanced Information
GS8170S18/36/72B-333/300/275/250
Special Functions
Burst Cycles
Although
Σ
RAMs can sustain 100% bus bandwidth by eliminating the bus turnaround cycle in both Late Write Flow through and
Double Late Write Pipelined modes, multiple back-to-back reads or writes may also be performed.
Σ
RAMs provide an on-chip
burst address generator that can be utilized, if desired, to further simplify burst read or write implementations. The ADV control
pin, when driven high, commands the SRAM to advance the internal address counter and use the counter generated address to read
or write the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin
low, into Load mode.
DA
DB
DE
DA
DC
F
/E
1
Write
B
C
D
ADV
Non-Write
Write
Write
CK
Address
A
E
Write
CQ
/BA
/BB
DQA0-DQA8
DQB0-DQB8
Byte Write Control Example with x18 Sigma Late Write RAM
相關PDF資料 |
PDF描述 |
|---|---|
| GS8170S72 | 16Mb（256K x 72Bit）Synchronous SRAM(16M位（256K x 72位）同步靜態(tài)RAM) |
| GS8180D09 | 2Mb x 9Bit Separate I/O Sigma DDR SRAM(2M x 9位獨立I/O接口雙數(shù)據(jù)速率讀和寫模式靜態(tài)ΣRAM) |
| GS8180D18 | 1Mb x 18Bit Separate I/O Sigma DDR SRAM(1M x 18位獨立I/O接口雙數(shù)據(jù)速率讀和寫模式靜態(tài)ΣRAM) |
| GS8180S36 | 512K x 36Bit Separate I/O Sigma DDR SRAM(512K x 36位獨立I/O接口雙數(shù)據(jù)速率讀和寫模式靜態(tài)ΣRAM) |
| GS8180S18 | 1Mb x 18Bit Separate I/O Sigma DDR SRAM(1M x 18位獨立I/O接口雙數(shù)據(jù)速率讀和寫模式靜態(tài)ΣRAM) |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| GS8171DW36AC-300I | 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V 18MBIT 512KX36 1.8NS 209FBGA - Trays |
| GS8171DW36AC-350 | 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V 18MBIT 512KX36 1.7NS 209FBGA - Trays |
| GS8171DW36AC-350I | 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V 18MBIT 512KX36 1.7NS 209BGA - Trays |
| GS8171DW36AGC-250 | 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V 18MBIT 512KX36 2.1NS 209FBGA - Trays |
| GS8171DW36AGC-300 | 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V 18MBIT 512KX36 1.8NS 209FBGA - Trays |
發(fā)布緊急采購，3分鐘左右您將得到回復。