
Signal Description
MOTOROLA
EC000 CORE PROCESSOR USER’S MANUAL
2-5
2.4.6 Read-Modify-Write (RMCB)
This active-low, three-state output line is logic low during read-modify-write cycles and indi-
cates an indivisible bus sequence. This is described in 3.1.3 Read-Modify-Write Cycle.
2.5 BUS ARBITRATION CONTROL
The bus request, bus grant, and bus grant acknowledge signals form the bus arbitration con-
trol signals that determine which device will be the bus master device. There are two possi-
ble arbitration protocols: 2-wire and 3-wire. In the 2-wire protocol, BGACKB is not used and
must be negated.
2.5.1 Bus Request (BRB)
This active-low input is the combination of bus request signals from all other devices that
could be bus masters. This signal indicates to the SCM68000 that some other device needs
to become the bus master. Bus requests can be issued at any time during a cycle or
between cycles.
2.5.2 Bus Grant (BGB)
This active-low output indicates to all other potential bus master devices that the SCM68000
will relinquish bus control at the end of the current bus cycle.
2.5.3 Bus Grant Acknowledge (BGACKB)—3-Wire Protocol Only
This active-low input indicates that some other device has become the bus master. This sig-
nal should not be asserted until the following four conditions are met:
1. A bus grant has been received.
2. Address strobe is negated, which indicates that the SCM68000 is not using the bus.
3. Data transfer acknowledge is negated, which indicates that neither memory nor pe-
ripherals are using the bus.
4. Bus grant acknowledge is negated, which indicates that no other device is still claiming
to be the bus master.
2.6 INTERRUPT CONTROL (IPLB2–IPLB0)
These active-low input signals indicate the encoded priority level of the device requesting
an interrupt. Level 7, which cannot be masked, has the highest priority; level 0 indicates that
no interrupts have been requested. IPLB0 is the least significant bit of the encoded level,
and IPLB2 is the most significant bit. For each interrupt request, these signals must maintain
the interrupt request level until the SCM68000 acknowledges the interrupt to guarantee that
Table 2-4. Data Transfer Size
Size Code Output
SIZ1
SIZ0
Size
1
0
Byte
0
1
Word
F
re
e
sc
a
le
S
e
m
ic
o
n
d
u
c
to
r,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
c
..
.