參數(shù)資料
型號: EC000UM
英文描述: EC000 Core User's Manual (SCM68000)
中文描述: EC000核心用戶手冊(SCM68000)
文件頁數(shù): 129/145頁
文件大?。?/td> 829K
代理商: EC000UM
Bus Operation
MOTOROLA
EC000 CORE PROCESSOR USER’S MANUAL
3-43
The negation of BERRB and HALTIB under several conditions is shown in Table 3-2.
DTACKB is assumed to be negated normally in all cases. For reliable operation, both
DTACKB and BERRB should be negated when address strobe is negated.
Table 3-2 shows when BERRB and HALTIB should be negated with respect to when they
were asserted to produce various results. The first column describes which case in Table 3-
1 is being used for asserting the signals. The third column shows the current bus state and
the fourth column shows the following bus state. The last column describes what will happen
in the next bus cycle given the conditions described in the previous columns.
Table 3-1. DTACKB, BERRB, and HALTIB Assertion Results
Case
No.
Control
Signal Input
Asserted on
Rising Edge of
State
*
Result
N
N+2
1
DTACKB
BERRB
HALTIB
A
NA
S
X
Normal cycle terminate and continue.
2
DTACKB
BERRB
HALTIB
A
NA
A/S
S
X
S
Normal cycle terminate and halt. Continue
when HALTIB negated.
3
DTACKB
BERRB
HALTIB
X
A
NA
X
S
NA
Terminate and take bus error trap.
4
DTACKB
BERRB
HALTIB
NA
A
NA
X
S
A
Terminate and retry when HALTIB negated.
5
DTACKB
BERRB
HALTIB
X
A
X
S
Terminate and retry when HALTIB negated.
6
DTACKB
BERRB
HALTIB
NA
A
X
A
S
Terminate and retry when HALTIB negated.
LEGEND:
N — The number of the current even bus state (e.g., S4, S6, etc.)
A — Signal asserted in this bus state
NA — Signal not asserted in this bus state
X — Don't care
S — Signal asserted in preceding bus state and remains asserted in this state
*The DTACKB, BERRB, and HALTIB signals are subject to the setup and hold time (spec
#47, defined in Section 7 Electrical Characteristics) before they are sampled on the
falling edge of the previous state. “Asserted” in this table refers to the time when the sig-
nals are valid internally. See 3.5 Asynchronous Operation for more details on external
asynchronous signal synchronization.
F
re
e
sc
a
le
S
e
m
ic
o
n
d
u
c
to
r,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
c
..
.
相關(guān)PDF資料
PDF描述
EC103B Sensitive SCRs
EC103B1 Sensitive SCRs
EC103B2 Sensitive SCRs
EC103B3 Sensitive SCRs
EC103D175 Thyristor Product Catalog
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EC0010-000 制造商:TE Connectivity 功能描述:EC0010-000
EC001031 制造商:PHOENIX 制造商全稱:PHOENIX CONTACT 功能描述:Header, Nominal current: 12 A, Rated voltage (III/2): 320 V, Assembly: Soldering
EC001121 制造商:PHOENIX 制造商全稱:PHOENIX CONTACT 功能描述:Plug component, Nominal current: 12 A, Rated voltage (III/2): 320 V, Number of positions: 4, Pitch: 5mm, Connection method: Screw connection, Color: Black, Contact surface: Tin
EC001283 制造商:PHOENIX 制造商全稱:PHOENIX CONTACT 功能描述:Plug component, Nominal current: 12 A, Rated voltage (III/2): 320 V, Number of positions: 7, Pitch: 5.08 mm, Connection method: Solder/Slip-on connection, Color: green, Contact surface: Tin, Assembly: Direct mounting
EC0013-000 制造商:TE Connectivity 功能描述:EC0013-000