參數(shù)資料
型號(hào)： EC000UM
英文描述： EC000 Core User＇s Manual (SCM68000)
中文描述： EC000核心用戶手冊(cè)（SCM68000）
文件頁數(shù)： 41/145頁
文件大?。?/td> 829K
代理商： EC000UM
Electrical Characteristics
7-6
EC000 CORE PROCESSOR USER’S MANUAL
MOTOROLA
7.7 AC ELECTRICAL SPECIFICATIONS—SCM68000 TO EXTERNAL
PERIPHERALS
(Frequency = 0 to 20 MHz; GND = 0 Vdc; TA = TL to TH; refer to Figure 7-4)
Num
Characteristic
3.3 V
5.0 V
Unit
Min
Max
Min
Max
12
Clock Low to ASB, DSB Negated
1
20
1
18
ns
18
Clock High to RWB High (Read)
0
20
0
18
ns
20
Clock High to RWB Low (Write)
0
20
0
20
ns
23
Clock Low to Data-Out Valid (Write)
—
20
—
18
ns
27
Data-In Valid to Clock Low (Setup Time on Read)
5—5—
ns
29
ASB, DSB Negated to Data-In Invalid (Hold Time on Read)
0—0—
ns
41
Clock Low to TESTCLK Transition
—
20
—
18
ns
42
TESTCLK Output Rise and Fall Time
—
12
—
12
ns
44
ASB, DSB Negated to AVECB Negated
0
42
0
42
ns
45
TESTCLK Low to Control, Address Bus Invalid (Address Hold
Time)
10—10—
ns
47
Asynchronous Input Setup Time
5—5—
ns
491
ASB, DSB Negated to TESTCLK Low
–30
30
–30
30
ns
50
TESTCLK Width High
190
—
190
—
ns
51
TESTCLK Width Low
290
—
290
—
ns
54
TESTCLK Low to Data-Out Invalid
5—5—
ns
NOTE:
1.The falling edge of S6 triggers both the negation of the strobes (ASB and DSB) and the falling edge of TESTCLK. Either
of these events can occur rst, depending upon the loading on each signal. Specicaton #49 indicates the absolute
maximum skew that will occur between the rising edge of the strobes and the falling edge of TESTCLK.
Figure 7-4. SCM68000 to External Peripherals Timing Diagram
S0
S1
S2
S3
S4
w
wwwwww
ww
S5
S6
S7
S0
A31–A0
CLKI
ASB
RWB
DATA OUT
DATA IN
23
18
41
20
42
51
47
50
42
41
12
49
18
44
45
41
54
29
27
45
TESTCLK
AVECB
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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