參數(shù)資料
型號(hào)： EC000UM
英文描述： EC000 Core User＇s Manual (SCM68000)
中文描述： EC000核心用戶手冊(cè)（SCM68000）
文件頁數(shù)： 19/145頁
文件大?。?/td> 829K
代理商： EC000UM
8-Bit Instruction Execution Times
5-6
EC000 CORE PROCESSOR USER’S MANUAL
MOTOROLA
5.6 SHIFT/ROTATE INSTRUCTION EXECUTION TIMES
Table 5-8 lists the timing data for the shift and rotate instructions. The total number of clock
periods, the number of read cycles, and the number of write cycles are shown in the previ-
ously described format. The number of clock periods, the number of read cycles, and the
number of write cycles, respectively, must be added to those of the effective address calcu-
lation where indicated by a plus sign (+).
5.7 BIT MANIPULATION INSTRUCTION EXECUTION TIMESS
Table 5-9 lists the timing data for the bit manipulation instructions. The total number of clock
periods, the number of read cycles, and the number of write cycles are shown in the previ-
ously described format. The number of clock periods, the number of read cycles, and the
number of write cycles, respectively, must be added to those of the effective address calcu-
lation where indicated by a plus sign (+).
5.8 CONDITIONAL INSTRUCTION EXECUTION TIMES
Table 5-10 lists the timing data for the conditional instructions. The total number of clock
periods, the number of read cycles, and the number of write cycles are shown in the previ-
ously described format. The number of clock periods, the number of read cycles, and the
number of write cycles, respectively, must be added to those of the effective address calcu-
lation where indicated by a plus sign (+).
Table 5-8. Shift/Rotate Instruction Execution Times
Instruction
Size
Register
Memory
ASR, ASL
Byte
Word
Long
10+2n(2/0)
12+n2(2/0)
—
16(2/2)+
—
LSR, LSL
Byte
Word
Long
10+2n(2/0)
12+n2(2/0)
—
16(2/2)+
—
ROR, ROL
Byte
Word
Long
10+2n(2/0)
12+n2(2/0)
—
16(2/2)+
—
ROXR, ROXL
Byte
Word
Long
10+2n(2/0)
12+n2(2/0)
—
16(2/2)+
—
+ Add effective address calculation time for word operands.
n is the shift count.
Table 5-9. Bit Manipulation Instruction Execution Times
Instruction
Size
Dynamic
Static
Register
Memory
Register
Memory
BCHG
Byte
Long
—
12(2/0)*
12(2/1)+
—
20(4/0)*
20(4/1)+
—
BCLR
Byte
Long
—
14(2/0)*
12(2/1)+
—
22(4/0)*
20(4/1)+
—
BSET
Byte
Long
—
12(2/0)*
12(2/1)+
—
20(4/0)*
20(4/1)+
—
BTST
Byte
Long
—
10(2/0)
8(2/0)+
—
18(4/0)
16(4/0)+
—
+ Add effective address calculation time.
* Indicates maximum value; data addressing mode only.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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