參數(shù)資料
型號(hào)： EC000UM
英文描述： EC000 Core User＇s Manual (SCM68000)
中文描述： EC000核心用戶手冊(cè)（SCM68000）
文件頁數(shù)： 65/145頁
文件大?。?/td> 829K
代理商： EC000UM
Overview
1-13
EC000 CORE PROCESSOR USER’S MANUAL
MOTOROLA
Table 1-2. Notational Conventions
Single- and Double-Operand Operations
≠
Not equal.
+
Arithmetic addition or postincrement indicator.
–
Arithmetic subtraction or predecrement indicator.
×
Arithmetic multiplication.
÷
Arithmetic division or conjunction symbol.
~
Invert; operand is logically complemented.
Λ
Logical AND
V
Logical OR
⊕
Logical exclusive OR
→
Source operand is moved to destination operand.
Two operands are exchanged.
<
Relational test; true if source operand is less than destination operand.
>
Relational test; true if source operand is greater than destination operand.
<operand>
Data used as an operand.
<operand> tested
Operand is compared to zero and the condition codes are set appropriately.
<operand> sign-ex-
tended <operand>
All bits of the upper portion are made equal to the high-order bit of the lower portion.
<operand> shifted by
<count>
The source operand is shifted by the number of count.
<operand> rotated by
<count>
The source operand is rotated by the number of count.
bit number of <oper-
and>
Selects a single bit of the operand.
Other Operations
TRAP
1
→ S-bit of SR;
SSP – 4
→ SSP; PC → (SSP); SSP – 2 → SSP;
SR
→ (SSP); Vector Address → PC
STOP
Enter the stopped state, waiting for interrupts.
<operand>10
The operand is BCD; operations are performed in decimal.
If <condition>
then <operations>
else <operations>
Test the condition. If true, the operations after “then” are performed. If the condition is false and
the optional “else” clause is present, the operations after “else” are performed. If the condition
is false and "else" is omitted, the instruction performs no operation. Refer to the Bcc instruction
description as an example.
Register Specification
An
Any Address Register n (example: A3 is address register 3)
Ax, Ay
Source and destination address registers, respectively.
Dn
Any Data Register n (example: D5 is data register 5)
Dx, Dy
Source and destination data registers, respectively.
Rn
Any Address or Data Register
Rx, Ry
Any source and destination registers, respectively.
Xn
Index Register—An, Dn, or suppressed.
Data Format and Type
<fmt>
Operand Data Format: Byte (B), Word (W), Long (L)
Subfields and Qualifiers
#<xxx> or #<data>
Immediate data following the instruction word(s).
( )
Identifies an indirect address in a register.
[ ]
Identifies an indirect address in memory.
dn
Displacement Value, n Bits Wide (example: d16 is a 16-bit displacement).
Register Names
CCR
Condition Code Register (lower byte of status register)
PC
Program Counter
SR
Status Register
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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