參數(shù)資料
型號(hào)： CH7002D-V
廠商： Electronic Theatre Controls, Inc.
英文描述： Scalable VGA to NTSC/PAL Encoder
中文描述： 可擴(kuò)展顯卡至NTSC / PAL編碼器
文件頁(yè)數(shù)： 7/36頁(yè)
文件大?。?/td> 199K
代理商： CH7002D-V
CHRONTEL
CH7002D
201-0000-029 Rev 6.1, 8/2/99
7
Clock Generation and Video Timing
All clock signals of the CH7002 are generated from the VGA synchronization inputs by a low-jitter, PLL circuit.
The VGA input and sync timing are illustrated in
Figures 3
,
5 and 6.
The VGA pixel clock is generated internally,
using the VGA horizontal sync signal, and is used for sampling the RGB inputs pixel-by-pixel, which aids in
preventing aliasing artifacts. All synchronization and color burst envelope pulses are internally generated, using
only the timing signals provided by the VGA synchronization inputs.
In situations where the CH7002 is placed next to a graphics controller (e.g. motherboard or add-in cards), the
graphics pixel clock can be provided to CH7002, directly from the graphics controller via pin XCLK. This
arrangement minimizes phase jitter of the system clock used in the encoder. See the sections on
Application
Information
and
Registers and Programming
for detailed information on how to connect and enable this function.
Figure 3: Typical VGA Input Timing
Figure 4: VGA Horizontal and Vertical Sync Input Timing
Note:
The values shown in Figures 4 and 5 represent typical timing parameters for VGA controllers operating in 640x480
resolution at 60 Hz, with the CH7002 in overscan mode. Other resolutions and display modes have different timing
requirements.
Figure 5: External Clock Input Timing
31.78
μ
s
25.42
μ
s
1.91
μ
s
0.64
μ
s
3.81
μ
s
ACTIVE VIDEO
H
R,G,B
DATA
Note:
The timing diagram shown is for 640 x 480, 60 Hz VGA mode
31.78
μ
s
63.56
μ
s
H
V *
(ACTIVE LOW)
HSYNC and
VSYNC
EXT
PCLK
t
1
V
SYNC
EXT
PCLK
t
2
HSYNC and
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