參數(shù)資料
型號(hào)： CH7002D-V
廠商： Electronic Theatre Controls, Inc.
英文描述： Scalable VGA to NTSC/PAL Encoder
中文描述： 可擴(kuò)展顯卡至NTSC / PAL編碼器
文件頁(yè)數(shù)： 26/36頁(yè)
文件大小： 199K
代理商： CH7002D-V
CHRONTEL
CH7002D
26 201-0000-029 Rev6.1, 8/2/99
The Connection Detect Register provides a means to sense the connection of a TV to either S-Video or composite
video outputs. The status bits, Y, C, and CVBS, correspond to both the DAC outputs for S-Video (Y and C outputs)
and composite video (CVBS). However, the values contained in these status bits ARE NOT VALID until a sensing
procedure is performed. Using this register requires a sequence of events to enable the sensing of outputs, then
reading out the applicable status bits. The detection sequence works as follows:
1. Set the SENSE bit to a 1. This forces a constant current output onto the Y, C, and CVBS outputs. Note that
during SENSE = 1, these 3 analog outputs are at steady state and no TV synchronization pulses are asserted.
2. Reset the SENSE bit to 0. This triggers a comparison between the voltage sensed on these analog outputs
and the reference value expected (Vthreshold = 1.235V). If the measured voltage is below this threshold
value, it is considered connected. If it is above this voltage, it is considered unconnected. During this step,
each of the three status bits corresponding to individual analog outputs will be set if they are NOT
CONNECTED.
3. Read the status bits. The status bits, Y, C, and CVBS (corresponding to S-Video Y and C outputs and
composite video) now contain valid information which can be read to determine which outputs are
connected to a TV. Again, a “0” indicates a valid connection, a “1” indicates an unconnected output.
Test Register
Symbol: TR
Address: 0AH
Bits: 8
The Test Register contains 8 bits which are reserved for implementing patterns and measurements for tests. Writing
a logical one into each bit, in this register, places the chip in a specific test mode. These test modes are not
documented for use herein, since they are used only for manufacturing test.
Address Register
Symbol: AR
Address: 0BH
Bits: 4
The Address Register points to the register currently being accessed. Since the most significant four bits of all
addresses are zero, this register contains only the four least significant bits, AR[3:0].
Bit:
7
T7
6
T6
5
T5
4
T4
3
T3
2
T2
1
T1
0
T0
Symbol:
Type:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default:
0
0
0
0
0
0
0
0
Bit:
Symbol:
7
6
5
4
3
AR3
2
AR2
1
AR1
0
AR0
Type:
Default:
R/W
R/W
R/W
R/W
0
0
0
0
X
X
X
X
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