參數(shù)資料
型號(hào)： CH7002D-V
廠商： Electronic Theatre Controls, Inc.
英文描述： Scalable VGA to NTSC/PAL Encoder
中文描述： 可擴(kuò)展顯卡至NTSC / PAL編碼器
文件頁(yè)數(shù)： 30/36頁(yè)
文件大?。?/td> 199K
代理商： CH7002D-V
CHRONTEL
CH7002D
30 201-0000-029 Rev6.1, 8/2/99
Position Control
The CH7002 defines four pins (UP, DOWN, LEFT, RIGHT) which provide a hardware-controlled positioning
mechanism to adjust the horizontal and vertical position of the output image on the television screen. These inputs
are rising edge-triggered, asynchronous, TTL-compatible inputs. They may be controlled from other logic devices
such as I/O ports or microcontrollers, or may be connected to SPST switches directly. The inputs include an on-chip
pull-up resistor so that only simple switch closures to ground are required. Care should be taken to avoid switch
bounce. Also, simultaneous assertion of more than one of the four inputs should be avoided.
Crystal Oscillator
The CH7002 includes an oscillator circuit which allows an inexpensive 14.31818 MHz crystal to be connected
directly. Alternatively, an externally generated 14.31818 MHz clock source may be supplied to the CH7002. If an
external source is used, it should have TTL level specifications. The clock should be connected to the XO/FIN pin
(pin 18), and the XI pin (pin 17) should be tied to ground. An external source should also exhibit +/- 50 ppm or
better frequent accuracy, and have low jitter characteristics.
If a crystal is used, the designer should ensure that the following conditions are met:
Crystal is specified as 14.31818 MHz, +/- 50 ppm in parallel resonance
Crystal is operated with a load capacitance equal to its specified value
External load capacitors have their ground connection very close to the CH7002
To allow tunability, a variable cap may be used from XI to ground
Note that the XI and XO/FIN pin each have approximately 15-10 pF of shunt capacitance internal to the device. To
calculate the proper external load capacitance to be added to the XI and XO/FIN pins, the following calculation
should be used:
Cext = (2 * Cload) - Cint
where external load capacitance shall include routing capacitance on the PCB:
Cext = External load capacitance required on XI and XO/FIN nodes
Cload = Crystal load capacitance specified by crystal manufacturer
Cint = Capacitance internal to CH7002 (approximately 15-10 pF on each of XI and
XO/FIN pins)
PC Board Layout Guidelines
The CH7002 is a high performance, mixed-signal IC containing precision analog and digital circuits. This section
provides general guidelines for CH7002 PCB layout. Information on the ground plane, power planes, power supply
decoupling, and layout for critical analog/digital signals and circuitry are included. The following design guidelines
are intended to optimize the layout for minimum signal coupling. These are only recommendations. The user is
urged to implement the configurations and evaluate the performance of the entire system before bringing the design
to production.
Two-Layer vs. Four-Layer Designs
The CH7002 can be successfully used in either double-sided PCB applications, or PCB designs using four (or more)
layers of interconnect. Using at least four layers will usually simplify the design task, and may also lower radiated
emissions. In either case, the use of ground and power planes are necessary to achieve full performance. Ground and
power planes should fill all available PCB areas not used for routing signals.
In the case of 4-layer designs, the recommended layer utilization is as follows:
Layer 1 (top): Analog interconnections
Layer 2: Ground plane
Layer 3: Power supply planes
Layer 4: Digital interconnections
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CH7004C-T 制造商:CHRONTEL 功能描述:
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