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參數資料
| 型號： | CH7002D-V |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Scalable VGA to NTSC/PAL Encoder |
| 中文描述： | 可擴展顯卡至NTSC / PAL編碼器 |
| 文件頁數： | 23/36頁 |
| 文件大?。?/td> | 199K |
| 代理商： | CH7002D-V |
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CHRONTEL
CH7002D
201-0000-029 Rev 6.1, 8/2/99
23
Register Descriptions (continued)
Flicker Filter Register
Symbol: FFR
Address: 01H
Bits: 2
The flicker filter register provides for flicker filter mode selection, only when operating in Overscan modes (display
modes 2 or 4). The low order bits of this register, FFR1 and FFR0, are logically “muxed” with the external pins
MS1 and MS0 respectively. Flicker filter bits, FFR[1:0], form a two-bit value which corresponds to the flicker
filter mode selection as follows:
Y (Luma) Filter Register
Symbol: YFR
Address: 02H
Bits: 3
This register enables the selection of alternative Luma filters for use with either composite or S-video outputs as
well as the disabling of the Y-peaking circuit. In the default condition, the CH7002 is setup to use lower bandwidth
filters with peaking enabled. Programming a “1” into each of these bit positions has the following effect:
Sampling Delay Register
Symbol: SDR
Address: 03H
Bits: 4
This register sets the delay timing, between the on-chip sampling clock and the sync signals, for the analog RGB
inputs. The four least significant bits of this register provide a programmable delay value, in 15 programmable
steps, with each step being 2.5 ns (nominal). As shown, the default value is 0 delay. Selecting a value of 4 creates a
delay of 10 ns and a value of 8 places; the sampling delay is at the opposite phase of sampling the input signals.
Bit:
7
6
5
4
3
2
1
FF1
0
FF0
Symbol:
Type:
R/W
R/W
Default:
0
1
FFR[1:0]
00
01
10
11
Mode
0:1:0
1:2:1
1:3:1
1:1:1
Comments
Flicker filtering is disabled
Moderate flicker filtering Default Mode
Low flicker filtering
High flicker filtering
Bit:
Symbol:
7
6
5
4
3
2
YPEAKD
1
YC-HI
0
YC-HI
Type:
Default:
R/W
R/W
R/W
0
0
0
Bit Position
CVBS-HI
YC-HI
Functional Description
Selects the high bandwidth filter for composite video outputs
Selects the high bandwidth filter for S-Video outputs and disables
the Y-peaking circuit
Disables the Y-peaking circuit
YPEAKD
Bit:
7
6
5
4
3
SD3
2
SD2
1
SD1
0
SD0
Symbol:
Type:
R/W
R/W
R/W
R/W
Default:
0
0
0
0
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