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參數(shù)資料
| 型號(hào)： | CH7002D-V |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Scalable VGA to NTSC/PAL Encoder |
| 中文描述： | 可擴(kuò)展顯卡至NTSC / PAL編碼器 |
| 文件頁數(shù)： | 29/36頁 |
| 文件大小： | 199K |
| 代理商： | CH7002D-V |
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CHRONTEL
CH7002D
201-0000-029 Rev 6.1, 8/2/99
29
Analog Output Connections
The Y (luminance), C (chrominance), and CVBS (composite video, blanking and sync) outputs are direct current
source outputs from the video DACs. An external shunt terminating resistor (nominally 75 ohms) is placed at the
DAC outputs and serves to convert the current output to a voltage. Proper NTSC and PAL format output levels are
achieved when the total effective termination is 37.5 ohms. External “reconstruction” filter networks are usually
used to create a smooth and bandlimited output waveform. A reconstruction filter is recommended on the CVBS out
to minimize image artifacts. The filters on the Y and C outputs often are not required and may unnecessarily limit
signal bandwidth.
Figure 25
shows a typical reconstruction filter structure and component values.
Figure 25: Typical Fourth-Order Reconstruction Filter
Control Interface
The operating modes of the CH7002 may be controlled either through dedicated digital input pins, or through the
I
2
C serial control interface. Selection of the control method is established by the PMODE pin; this pin should be
strapped to either DVDD or GND, when the device is powered up, and should not be changed during operation.
When PMODE=1, the I
2
C interface is enabled. Both of the SD/DM1 and SC/DM2 pins become the Serial Data and
Serial Clock signals for the two-wire I
2
C interface.
When PMODE= 0, the following pin functions are defined as:
RESET*/DM0 becomes an input selecting CH7002 operating mode
SD/DM1 becomes an input selecting CH7002 operating mode
SC/DM2 becomes an input selecting CH7002 operating mode
ADDR/FF0 becomes an input selecting CH7002 deflicker mode
XCLK/SD3 becomes an input, selecting one of two analog input sample points
When pin control mode (PMODE=0) is selected, the function of the SC/DM2, SD/DM1, and RESET*/DM0 pins is
identical to that of bits DM2, DM1, DM0 in configuration register DMR (Display Mode Register). The encoding of
these inputs is restated in Table 6.
Table 6. Encoding Inputs Pin Control Mode
DM2
DM1
DM0
Input Resolution
Output Format
Scaling
0
0
0
800x600
PAL
Underscan
0
0
1
640X480
PAL
Underscan
0
1
0
640X480
NTSC
Overscan
0
1
1
640X480
NTSC
Underscan
1
0
0
640X480
PAL
Overscan
1
0
1
800X600
PAL
Overscan
1
1
0
800X600
NTSC
Underscan
1
1
1
Power Down
None
None
1.2uH
1.2uH
150pF
270pF
47pF
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