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參數(shù)資料
| 型號： | CH7002D-V |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Scalable VGA to NTSC/PAL Encoder |
| 中文描述： | 可擴展顯卡至NTSC / PAL編碼器 |
| 文件頁數(shù)： | 25/36頁 |
| 文件大小： | 199K |
| 代理商： | CH7002D-V |
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CHRONTEL
CH7002D
201-0000-029 Rev 6.1, 8/2/99
25
Register Descriptions (continued)
Miscellaneous Control Register
Symbol: MCR
Address: 08H
Bits: 8
This register provides control of a number of different and unrelated functions, segmented into the following:
Power Down
- The CH7002 provides programmable control of its operating states, including normal and three
reduced power modes. Bits 0 and 1 of MCR setup these modes as follows:
Scratchpad Bits
- One bit has been set aside as a scratchpad bit, with no on-chip control functions as a convenience
for programming.
Control Bits
- Several control bits are provided to enable/disable specific video control functions:
Connection Detect Register
Symbol: CDR
Address: 09H
Bits: 4
Bit:
Symbol:
7
CEE
6
BUD
5
ECE
4
ECD2
3
SP0
2
Reserved
1
PD1
0
PD0
Type:
Default:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
1
1
PD[1:0]
11
10
Operating State
Normal (On):
S-Video Off:
Functional Description
All circuits and pins are active
Power is shut off to the unused DACs associated with Y and
C outputs
Most pins and circuitry are disabled (except for the bandgap
reference)
Power is shut off to the unused DAC associated with CVBS
output
01
Power Down:
00
Composite Off:
Symbol
ECE
Functional Description
External Clock Enable. Setting this bit enables the external clock
input on the XCLK pin
Burst Update Clock Disable. Setting this bit disables the burst
frequency counter updates
Contrast Enhancement Enable. Setting this bit enables a contrast
enhancement circuit
External clock divide by two enable. Setting this bit enables
dividing the incoming pixel clock by two.
BUD
CEE
ECD2
Bit:
7
6
5
4
3
Y
2
C
1
CVBS
0
SENSE
Symbol:
Type:
R
R
R
W
Default:
0
0
0
0
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