參數(shù)資料
型號: CH7002D-V
廠商: Electronic Theatre Controls, Inc.
英文描述: Scalable VGA to NTSC/PAL Encoder
中文描述: 可擴展顯卡至NTSC / PAL編碼器
文件頁數(shù): 24/36頁
文件大?。?/td> 199K
代理商: CH7002D-V
CHRONTEL
CH7002D
24 201-0000-029 Rev6.1, 8/2/99
Register Descriptions (continued)
Black Level Register
Symbol: BLR
Address: 04H
Bits: 7
This register sets the black level, which is used as a relative baseline to reference the range of luminance values to
be output. The first seven bits of this register, BL[6:0], provide a programmable black level value, which must be set
between 51 and 80 (S-Video has limitation above 80), with the default of 61.
Position Control Register
Symbol: PCR
Address: 05H
Bits: 4
This register is used to shift the displayed TV image, in any orthogonal direction (left or right and up or down), to
achieve a centered image on screen. Each of the first four bits of this register, DOWN, UP, LEFT, AND RIGHT,
correspond to one of the basic directions of movement. As any of these bits are toggled (from 1 to 0 and back to 1),
the displayed image shifts four pixels in that direction from its current location (e.g. toggling UP will move the TV
image up by 4 input pixels). These four directional bits are bit-wise “ANDed,” with the signals from the four
corresponding input pins, so that position control can be effected at any time by using programming or toggle
switches. Note that the image positioning will be reset (to initial condition) by toggling into certain display modes.
When operating in modes 1 to 6, entering into mode 0 and returning will reset positioning. When operating in mode
0, entering into mode 1 and returning will also reset positioning. Resetting the position can be used to enable
absolute position programming by starting from a known reference.
Version ID Register
Symbol: VIR
Address: 07H
Bits: 3
This read-only register contains a 3-bit value, indicating the identification number, assigned to this version of the
CH7002. The default value shown is pre-programmed into this chip and is useful for checking the correct version
of this chip before proceeding with its programming.
Bit:
7
6
BL6
5
BL5
4
BL4
3
BL3
2
BL2
1
BL1
0
BL0
Symbol:
Type:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default:
0
1
1
1
1
0
1
Bit:
Symbol:
7
6
5
4
3
LEFT
2
RIGHT
1
UP
0
DOWN
Type:
Default:
W
W
W
W
1
1
1
1
Bit:
7
6
5
4
3
2
VIR3
1
VIR1
0
VIR0
Symbol:
Type:
R
R
R
Default:
0
0
0
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