參數(shù)資料
型號: BXM80526B700128
英文描述: Octal bus buffer with 3 state outputs (inverted)
中文描述: 微處理器
文件頁數(shù): 77/81頁
文件大?。?/td> 598K
代理商: BXM80526B700128
Mobile Intel
Celeron Processor (0.18μ) in BGA2 and Micro-PGA2 Packages
Order Number#249563-001
Datasheet
77
Table 38. Output Signals
Name
Active Level
Clock
Signal Group
FERR#
Low
Asynch
Open-drain
IERR#
Low
Asynch
Open-drain
PRDY#
Low
BCLK
Implementation
TDO
High
TCK
JTAG
VID[4:0]
High
Asynch
Implementation
Table 39. Input/Output Signals (Single Driver)
Name
Active Level
Clock
Signal Group
Qualified
A[35:3]#
Low
BCLK
System Bus
ADS#, ADS#+1
ADS#
Low
BCLK
System Bus
Always
AP[1:0]#
Low
BCLK
System Bus
ADS#, ADS#+1
BREQ0#
Low
BCLK
System Bus
Always
BP[3:2]#
Low
BCLK
System Bus
Always
BPM[1:0]#
Low
BCLK
System Bus
Always
D[63:0]#
Low
BCLK
System Bus
DRDY#
DBSY#
Low
BCLK
System Bus
Always
DEP[7:0]#
Low
BCLK
System Bus
DRDY#
DRDY#
Low
BCLK
System Bus
Always
LOCK#
Low
BCLK
System Bus
Always
REQ[4:0]#
Low
BCLK
System Bus
ADS#, ADS#+1
RP#
Low
BCLK
System Bus
ADS#, ADS#+1
Table 40. Input/Output Signals (Multiple Driver)
Name
Active Level
Clock
Signal Group
Qualified
AERR#
Low
BCLK
System Bus
ADS#+3
BERR#
Low
BCLK
System Bus
Always
BINIT#
Low
BCLK
System Bus
Always
BNR#
Low
BCLK
System Bus
Always
HIT#
Low
BCLK
System Bus
Always
HITM#
Low
BCLK
System Bus
Always
PICD[1:0]
High
PICCLK
APIC
Always
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