參數(shù)資料
型號： BXM80526B700128
英文描述： Octal bus buffer with 3 state outputs (inverted)
中文描述： 微處理器
文件頁數(shù)： 6/81頁
文件大小： 598K
代理商： BXM80526B700128
Mobile Intel
Celeron Processor (0.18μ) in BGA2 and Micro-PGA2 Packages
Datasheet
Order Number#249563-001
6
Figures
Figure 1. Signal Groups of a Mobile Intel Celeron Processor/440MX Chipset - Based
System
....................................................................................................................9
Figure 2. Clock Control States
......................................................................................14
Figure 3. Vcc Ramp Rate Requirement
.........................................................................19
Figure 4. PLL RLC Filter
...............................................................................................22
Figure 5. PICCLK/TCK Clock Timing Waveform
............................................................34
Figure 6. BCLK Timing Waveform
.................................................................................34
Figure 7. Valid Delay Timings
.......................................................................................35
Figure 8. Setup and Hold Timings
.................................................................................35
Figure 9. Cold/Warm Reset and Configuration Timings
.................................................36
Figure 10. Power-on Reset Timings
..............................................................................36
Figure 11. Test Timings (Boundary Scan)
.....................................................................37
Figure 12. Test Reset Timings
......................................................................................37
Figure 13. Quick Start/Deep Sleep Timing
....................................................................38
Figure 14. Stop Grant/Sleep/Deep Sleep Timing
...........................................................39
Figure 15. BCLK/PICCLK Generic Clock Waveform
......................................................41
Figure 16. Low to High, GTL+ Receiver Ringback Tolerance
.........................................42
Figure 17. High to Low, GTL+ Receiver Ringback Tolerance
.........................................43
Figure 18. Maximum Acceptable Overshoot/Undershoot Waveform
..............................44
Figure 19. Surface-mount BGA2 Package - Top and Side View
.....................................47
Figure 20. Surface-mount BGA2 Package - Bottom View
..............................................48
Figure 21. Socketable Micro-PGA2 Package - Top and Side View
................................50
Figure 22. Socketable Micro-PGA2 Package - Bottom View
..........................................51
Figure 23. Pin/Ball Map - Top View
...............................................................................52
Figure 24. PWRGOOD Relationship at Power On
.........................................................71
Figure 25. PLL Filter Specifications
...............................................................................79
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