參數(shù)資料
型號(hào): BXM80526B700128
英文描述: Octal bus buffer with 3 state outputs (inverted)
中文描述: 微處理器
文件頁數(shù): 39/81頁
文件大?。?/td> 598K
代理商: BXM80526B700128
Mobile Intel
Celeron Processor (0.18μ) in BGA2 and Micro-PGA2 Packages
Order Number#249563-001
Datasheet
39
Figure 14. Stop Grant/Sleep/Deep Sleep Timing
T
u
stpgnt
Running
BCLK
STPCLK#
CPU bus
SLP#
Compatibility
Signals
Frozen
Changing
Normal
Stop
Grant
Sleep
Deep Sleep
Sleep
Stop
Grant
Normal
Running
T
t
T
v
T
y
T
z
T
w
T
x
V0011-00
Changing
NOTES:
T
t
T
u
T
v
T
w
T
x
T
y
T
z
=
=
=
=
=
=
=
T50 (Stop Grant Acknowledge Bus Cycle Completion to SLP# Assertion Delay)
T51 (Setup Time to Input Signal Hold Requirement)
T52 (SLP# assertion to clock shut off delay)
T47 (Deep Sleep PLL lock latency)
T54 (SLP# Hold Time)
T55 (STPCLK# Hold Time)
T56 (Input Signal Hold Time)
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