參數(shù)資料
型號(hào)： BXM80526B700128
英文描述： Octal bus buffer with 3 state outputs (inverted)
中文描述： 微處理器
文件頁(yè)數(shù)： 65/81頁(yè)
文件大小： 598K
代理商： BXM80526B700128
Mobile Intel
Celeron Processor (0.18μ) in BGA2 and Micro-PGA2 Packages
Order Number#249563-001
Datasheet
65
AP[1:0]# (I/O - GTL+)
The AP[1:0]# (Address Parity) signals are driven by the request initiator along with ADS#,
A[35:3]#, REQ[4:0]# and RP#. AP1# covers A[35:24]#. AP0# covers A[23:3]#. A correct parity
signal is high if an even number of covered signals are low and low if an odd number of covered
signals are low. This allows parity to be high when all the covered signals are high. AP[1:0]#
should be connected to the appropriate pins/balls on both agents on the system bus.
BCLK (I - 2.5V Tolerant)
The BCLK (Bus Clock) signal determines the system bus frequency. Both system bus agents must
receive this signal to drive their outputs and latch their inputs on the BCLK rising edge. All
external timing parameters are specified with respect to the BCLK signal.
BERR# (I/O - GTL+)
The BERR# (Bus Error) signal is asserted to indicate an unrecoverable error without a bus
protocol violation. It may be driven by either system bus agent and must be connected to the
appropriate pins/balls of both agents, if used. However, the mobile Intel Celeron processors do not
observe assertions of the BERR# signal.
BERR# assertion conditions are defined by the system configuration. Configuration options
enable the BERR# driver as follows:
Enabled or disabled
Asserted optionally for internal errors along with IERR#
Asserted optionally by the request initiator of a bus transaction after it observes an error
Asserted by any bus agent when it observes an error in a bus transaction
BINIT# (I/O - GTL+)
The BINIT# (Bus Initialization) signal may be observed and driven by both system bus agents and
must be connected to the appropriate pins/balls of both agents, if used. If the BINIT# driver is
enabled during the power-on configuration, BINIT# is asserted to signal any bus condition that
prevents reliable future information.
If BINIT# is enabled during power-on configuration, and BINIT# is sampled asserted, all bus state
machines are reset and any data which was in transit is lost. All agents reset their rotating ID for
bus arbitration to the state after reset, and internal count information is lost. The L1 and L2 caches
are not affected.
If BINIT# is disabled during power-on configuration, a central agent may handle an assertion of
BINIT# as appropriate to the Machine Check Architecture (MCA) of the system.
相關(guān)PDF資料
PDF描述
BXM80532GC1600D Octal bus buffer with 3 state outputs (inverted)
BXM80532GC1700D Microprocessor
BXM80532GC1800D Microprocessor
BXM80533B866128 Microprocessor
BXM80533B933128 Microprocessor
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
BXM80536NC1400ES L7LS 制造商:Intel 功能描述:CELERON M,360,1.40GHZ,1M CACHE, 400MHZ FSB,1.26V,UFCPGA - Boxed Product (Development Kits)
BXMP1000 制造商:SPECTRUM 制造商全稱(chēng):Spectrum Microwave, Inc. 功能描述:RF AMPLIFIER
BXMP1001 制造商:SPECTRUM 制造商全稱(chēng):Spectrum Microwave, Inc. 功能描述:RF AMPLIFIER
BXMP1002 制造商:SPECTRUM 制造商全稱(chēng):Spectrum Microwave, Inc. 功能描述:RF AMPLIFIER
BXMP1003 制造商:SPECTRUM 制造商全稱(chēng):Spectrum Microwave, Inc. 功能描述:RF AMPLIFIER
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*