參數(shù)資料
型號： AT85C51SND3B1-RTTUL
廠商： Atmel
文件頁數(shù)： 37/119頁
文件大?。?/td> 0K
描述： IC DECODER/ENCODER DGTL 100-LQFP
標準包裝： 90
類型： 音頻編碼器/解碼器
應(yīng)用： 移動電話，手機，視頻顯示器
電壓 - 電源，數(shù)字： 1.65 V ~ 3.6 V
安裝類型： 表面貼裝
封裝/外殼： 100-LQFP
供應(yīng)商設(shè)備封裝： 100-LQFP（14x14）
包裝： 托盤
24
AT85C51SND3B
7632D–MP3–01/07
Reset
In order to secure the product functionality while in power-up or power-down phase or
while in running phase, a number of internal mechanisms have been implemented.
These mechanisms are listed below and detailed in the following paragraphs.
External RST input
Power Fail Detector (brown-out)
Watchdog timer
Pads control
Figure 12 details the internal reset circuitry.
Reset Source Reporting
In order for the firmware to take specific actions depending on the source which has cur-
rently reset the device, activated reset source is reported to the CPU by EXTRST,
WDTRST, and PFDRST flags in PSTA register.
Figure 12. Internal Reset Circuitry
Pads Level Control
As soon as one reset source is asserted, the pads go to their reset value. This ensures
that pads level is steady during reset (e.g. NFWP set to low level and then protecting
Nand Flash against spurious writing).
The status of the Port pins during reset is detailed in Table 19.
Table 19. Pin State Under Reset Condition.
External RST Input
In order to start-up (cold reset) or to restart (warm reset) properly the microcontroller, a
low level has to be applied on the RST pin. A bad level leads to a wrong initialization of
the internal registers like SFRs, Program Counter… and to unpredictable behavior of
the microcontroller. A proper device reset initializes the AT85C51SND3B and vectors
the CPU to address 0000h. RST input has a pull-up resistor allowing power-on reset by
simply connecting an external capacitor to VSS as shown in Figure 13. A warm reset can
be applied either directly on the RST pin or indirectly by an internal reset source such as
the watchdog timer. Resistor value and input characteristics are discussed in the
Section “DC Characteristics”, page 242.
RST
To CPU Core
IOVDD
DCPWR
DC-DC
ON/OFF
VBAT
PFD
To Peripherals
To Pads Control
WDT
TO
SYSRST
OUT
EXTRST
PSTA.1
WDTRST
PSTA.2
PFDRST
PSTA.0
LVDD
RRST
HVDD
1.8V
Reg
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
NFD7:0
NFWP
NFCE0
Float
H
Float
L
H
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