參數(shù)資料
型號： AT85C51SND3B1-RTTUL
廠商： Atmel
文件頁數(shù)： 20/119頁
文件大?。?/td> 0K
描述： IC DECODER/ENCODER DGTL 100-LQFP
標(biāo)準(zhǔn)包裝： 90
類型： 音頻編碼器/解碼器
應(yīng)用： 移動電話，手機(jī)，視頻顯示器
電壓 - 電源，數(shù)字： 1.65 V ~ 3.6 V
安裝類型： 表面貼裝
封裝/外殼： 100-LQFP
供應(yīng)商設(shè)備封裝： 100-LQFP（14x14）
包裝： 托盤
116
AT85C51SND3B
7632D–MP3–01/07
Reset Value = 0000 0000b
3
EORSTI
End Of Reset Interrupt Flag
Set by hardware when an “End Of Reset” has been detected by the USB
controller. This triggers an USB interrupt if EORSTE is set.
Shall be cleared by software. Setting by software has no effect.
2
SOFI
Start Of Frame Interrupt Flag
Set by hardware when an USB “Start Of Frame” PID (SOF) has been detected
(every 1 ms). This triggers an USB interrupt if SOFE is set.
1
MSOFI
Micro-Start Of Frame Interrupt Flag
Set by hardware when an USB “Micro-Start Of Frame” PID (SOF) has been
detected (every 125 s). This triggers an USB interrupt if MSOFE is set.
0
SUSPI
Suspend Interrupt Flag
Set by hardware when an USB “Suspend” ‘idle bus for 3 frame periods: a J state
for 3 ms) is detected. This triggers an USB interrupt if SUSPE is set.
Shall be cleared by software. Setting by software has no effect.
Table 114. UDIEN Register
UDIEN (1.DAh) – USB Device Global Interrupt Enable Register
7
6
5
4
3
2
1
0
-
UPRSME
EORSME
WAKEUPE
EORSTE
SOFE
MSOFE
SUSPE
Bit
Number
Bit
Mnemonic Description
7
-
Reserved
The value read from these bits is always 0. Do not set these bits.
6
UPRSME
Upstream Resume Interrupt Enable Bit
Set to enable the UPRSMI interrupt.
Clear to disable the UPRSMI interrupt.
5
EORSME
End Of Resume Interrupt Enable Bit
Set to enable the EORSMI interrupt.
Clear to disable the EORSMI interrupt.
4
WAKEUPE
Wake-Up CPU Interrupt Enable Bit
Set to enable the WAKEUPI interrupt.
Clear to disable the WAKEUPI interrupt.
3
EORSTE
End Of Reset Interrupt Enable Bit
Set to enable the EORSTI interrupt. This bit is set after a reset.
Clear to disable the EORSTI interrupt.
2
SOFE
Start Of Frame Interrupt Enable Bit
Set to enable the SOFI interrupt.
Clear to disable the SOFI interrupt.
1
MSOFE
Micro-Start Of Frame Interrupt Enable Bit
Set to enable the MSOFI interrupt.
Clear to disable the MSOFI interrupt.
Bit
Number
Bit
Mnemonic Description
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